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    Searched refs:getUndefRegState (Results 1 - 17 of 17) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstrBuilder.h 514 inline unsigned getUndefRegState(bool B) {
532 getUndefRegState(RegOp.isUndef()) |
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineInstrBundle.cpp 223 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
SplitKit.cpp 528 .addReg(ToReg, RegState::Define | getUndefRegState(FirstCopy)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIOptimizeExecMaskingPreRA.cpp 193 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
AMDGPUInstructionSelector.cpp 526 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
SIInstrInfo.cpp 5150 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef());
SIISelLowering.cpp 3525 .addReg(Idx.getReg(), getUndefRegState(Idx.isUndef()));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 636 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
640 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
651 unsigned Flags = getUndefRegState(RO.isUndef());
675 unsigned Flags = getUndefRegState(RO.isUndef());
881 unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
882 unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
1057 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
1058 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 1741 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1749 .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
1750 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1820 getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
1822 getKillRegState(OddDeadKill) | getUndefRegState(OddUndef))
ARMExpandPseudoInsts.cpp 688 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
690 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
692 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
694 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
772 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
ARMBaseInstrInfo.cpp 5098 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
5134 .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
5168 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
5172 NewMIB.addReg(CurReg, getUndefRegState(CurUndef))
5186 MIB.addReg(CurReg, getUndefRegState(CurUndef));
5190 MIB.addReg(CurReg, getUndefRegState(CurUndef))
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.cpp 80 unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
263 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
268 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRegStackify.cpp 646 .addReg(DefReg, getUndefRegState(DefMO.isDead()));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRExpandPseudoInsts.cpp 1066 .addReg(DstReg, getUndefRegState(DstIsUndef))
1070 .addReg(DstReg, getUndefRegState(DstIsUndef))
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FrameLowering.cpp 301 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
X86InstrInfo.cpp 4663 getUndefRegState(MIB->getOperand(1).isUndef()));
6346 getUndefRegState(ImpOp.isUndef()));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 3745 .addReg(DestReg0, RegState::Define | getUndefRegState(IsUndef), SubIdx0)
3746 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1)

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