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    Searched refs:getVGPRClassForBitWidth (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.h 141 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const;
SIRegisterInfo.cpp 1910 SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) const {
2085 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size);
2099 assert(getVGPRClassForBitWidth(Size) && "Invalid register class size");
2108 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size);
2146 RC = getVGPRClassForBitWidth(Size);
2331 return getVGPRClassForBitWidth(std::max(32u, Size));
2458 return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC)));
SIISelLowering.cpp 93 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));
99 addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128));
102 addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160));
105 addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256));
108 addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256));
111 addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512));
114 addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));
117 addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));
131 addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024));
11534 RC = TRI->getVGPRClassForBitWidth(BitWidth)
    [all...]
SILoadStoreOptimizer.cpp 1597 : TRI->getVGPRClassForBitWidth(BitWidth);

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