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    Searched refs:getVRegDef (Results 1 - 25 of 83) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
InstructionSelector.cpp 50 MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
55 MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
Utils.cpp 83 MachineInstr *RegDef = MRI.getVRegDef(Reg);
315 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) &&
370 MachineInstr *MI = MRI.getVRegDef(VReg);
378 MachineInstr *MI = MRI.getVRegDef(VReg);
387 auto *DefMI = MRI.getVRegDef(Reg);
397 DefMI = MRI.getVRegDef(SrcReg);
548 const MachineInstr *DefMI = MRI.getVRegDef(Val);
635 MachineInstr *Def = MRI.getVRegDef(LiveIn);
GISelKnownBits.cpp 35 const MachineInstr *MI = MRI.getVRegDef(R);
119 MachineInstr &MI = *MRI.getVRegDef(R);
521 MachineInstr &MI = *MRI.getVRegDef(R);
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFMIPeephole.cpp 107 MachineInstr *DefInsn = MRI->getVRegDef(Reg);
122 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg());
161 MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg());
196 MachineInstr *SllMI = MRI->getVRegDef(ShfReg);
210 MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg());
481 MI2 = MRI->getVRegDef(SrcReg);
491 DefMI = MRI->getVRegDef(SrcReg);
498 DefMI = MRI->getVRegDef(SrcReg);
524 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg());
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 94 MachineInstr *DefMI = MRI->getVRegDef(Reg);
101 DefMI = MRI->getVRegDef(Reg);
107 DefMI = MRI->getVRegDef(Reg);
146 MachineInstr *DefMI = MRI->getVRegDef(Reg);
157 DefMI = MRI->getVRegDef(SrcReg);
165 DefMI = MRI->getVRegDef(Reg);
171 DefMI = MRI->getVRegDef(Reg);
A15SDOptimizer.cpp 157 MachineInstr *MI = MRI->getVRegDef(SReg);
251 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
252 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
303 MachineInstr *Def = MRI->getVRegDef(OpReg);
346 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
374 MachineInstr *NewMI = MRI->getVRegDef(Reg);
382 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
605 MachineInstr *Def = MRI->getVRegDef(*I);
MVETPAndVPTOptimisationsPass.cpp 99 MI = MRI->getVRegDef(MI->getOperand(1).getReg());
148 LookThroughCOPY(MRI->getVRegDef(LoopEnd->getOperand(0).getReg()), MRI);
157 LookThroughCOPY(MRI->getVRegDef(LoopDec->getOperand(1).getReg()), MRI);
170 LoopStart = LookThroughCOPY(MRI->getVRegDef(StartReg), MRI);
469 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI);
898 MachineInstr *Copy = MRI->getVRegDef(VPR);
909 MachineInstr *Def = MRI->getVRegDef(GPR);
927 DeadInstructions.insert(MRI->getVRegDef(GPR));
944 DeadInstructions.insert(MRI->getVRegDef(GPR));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonHardwareLoops.cpp 440 MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
448 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
466 MachineInstr *PredI = MRI->getVRegDef(PredR);
502 IVOp = MRI->getVRegDef(F->first);
605 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg);
651 MachineInstr *CondI = MRI->getVRegDef(PredReg);
699 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
705 OldInsts.push_back(MRI->getVRegDef(R));
709 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
715 OldInsts.push_back(MRI->getVRegDef(R))
    [all...]
HexagonVExtract.cpp 78 MachineInstr *DI = MRI.getVRegDef(ExtIdxR);
149 MachineInstr *DefI = MRI.getVRegDef(VecR);
183 MachineInstr *AlignaI = MRI.getVRegDef(AR);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCMIPeephole.cpp 164 return MRI->getVRegDef(Reg);
290 MachineInstr *Instr = MRI->getVRegDef(RegOp);
335 MachineInstr *PHIInput = MRI->getVRegDef(RegOp);
452 MachineInstr *RootPHI = MRI->getVRegDef(Src);
518 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
535 MachineInstr *LoadMI = MRI->getVRegDef(FeedReg1);
628 MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
638 MachineInstr *Splt = MRI->getVRegDef(ConvReg);
691 MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
703 MachineInstr *P1 = MRI->getVRegDef(DefsReg1)
    [all...]
PPCBranchCoalescing.cpp 367 MachineInstr *Op1Def = MRI->getVRegDef(Op1.getReg());
368 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg());
467 MachineInstr *DefInst = MRI->getVRegDef(Use.getReg());
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineLoopInfo.cpp 192 assert(MRI->getVRegDef(Reg) &&
197 if (contains(MRI->getVRegDef(Reg)))
OptimizePHIs.cpp 116 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
123 SrcMI = MRI->getVRegDef(SrcReg);
ModuloSchedule.cpp 399 int LoopValStage = Schedule.getStage(MRI.getVRegDef(LoopVal));
450 MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1);
458 InstOp1 = MRI.getVRegDef(PhiOp1);
472 if (MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1))
476 MachineInstr *PhiInst = MRI.getVRegDef(LoopVal);
643 if (MachineInstr *InstOp2 = MRI.getVRegDef(PhiOp2))
654 if (MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1)) {
800 MachineInstr *MI = MRI.getVRegDef(LCDef);
930 MachineInstr *BaseDef = MRI.getVRegDef(BaseReg);
933 BaseDef = MRI.getVRegDef(BaseReg)
    [all...]
MIRVRegNamerUtils.cpp 81 return MRI.getVRegDef(MO.getReg())->getOpcode();
141 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg));
MachineStableHash.cpp 67 return MRI.getVRegDef(MO.getReg())->getOpcode();
LiveVariables.cpp 130 assert(MRI->getVRegDef(Reg) && "Register use before def!");
165 if (MBB == MRI->getVRegDef(Reg)->getParent())
176 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), Pred);
591 MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getVRegDef(I)->getParent(),
653 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
724 const MachineInstr *Def = MRI.getVRegDef(Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyFixBrTableDefaults.cpp 61 auto ExtMI = MF.getRegInfo().getVRegDef(MI.getOperand(0).getReg());
123 auto *RangeCheck = MRI.getVRegDef(Cond[1].getReg());
WebAssemblyLowerBrUnless.cpp 77 MachineInstr *Def = MRI.getVRegDef(Cond);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizationArtifactCombiner.h 66 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
84 auto *SrcMI = MRI.getVRegDef(SrcReg);
127 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
139 markDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
144 auto *SrcMI = MRI.getVRegDef(SrcReg);
180 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
194 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
199 auto *SrcMI = MRI.getVRegDef(SrcReg);
226 auto *SrcMI = MRI.getVRegDef(SrcReg);
309 markInstAndDefDead(MI, *MRI.getVRegDef(TruncSrc), DeadInsts)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerCombiner.cpp 76 MachineInstr *Other = MRI.getVRegDef(Src1Op1);
79 Other = MRI.getVRegDef(Src1Op2);
84 Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) {
112 unsigned Opc = MRI.getVRegDef(R)->getOpcode();
118 return MRI.getVRegDef(R)->getOpcode() == TargetOpcode::G_ZEXT;
AArch64RegisterBankInfo.cpp 519 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
690 auto ScalarDef = MRI.getVRegDef(ScalarReg);
774 MachineInstr *DefMI = MRI.getVRegDef(VReg);
823 MachineInstr *DefMI = MRI.getVRegDef(VReg);
903 MachineInstr *DefMI = MRI.getVRegDef(VReg);
907 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVMergeBaseOffset.cpp 146 MachineInstr &OffsetTail = *MRI->getVRegDef(Reg);
155 *MRI->getVRegDef(OffsetTail.getOperand(1).getReg());
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXReplaceImageHandles.cpp 140 MachineInstr &TexHandleDef = *MRI.getVRegDef(Op.getReg());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFixSGPRCopies.cpp 625 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
736 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg());
827 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(I).getReg());
836 MachineInstr *Def = MRI->getVRegDef(InputReg);
851 MachineInstr *SrcDef = MRI->getVRegDef(SrcReg);

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