| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_hw_sequencer.c | 84 chunk_int = get_reg_field_value(
89 chunk_mul = get_reg_field_value(
|
| amdgpu_dce112_compressor.c | 308 if (get_reg_field_value(
455 if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
462 if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
465 if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
481 return get_reg_field_value(
636 channels = get_reg_field_value(value_control,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_timing_generator.c | 100 field = get_reg_field_value(value, CRTC0_CRTC_STATUS, CRTC_V_BLANK);
182 uint32_t field = get_reg_field_value(
199 position->horizontal_count = get_reg_field_value(value,
202 position->vertical_count = get_reg_field_value(value,
210 position->nominal_vcount = get_reg_field_value(value,
261 get_reg_field_value(value_crtc_vtotal,
324 if (get_reg_field_value(pol_value,
384 return get_reg_field_value(value,
618 position->horizontal_count = get_reg_field_value(
623 position->vertical_count = get_reg_field_value(
[all...] |
| amdgpu_dce120_hw_sequencer.c | 120 chunk_int = get_reg_field_value(
125 chunk_mul = get_reg_field_value(
|
| amdgpu_dce120_resource.c | 669 straps->audio_stream_number = get_reg_field_value(reg_val,
672 straps->hdmi_disable = get_reg_field_value(reg_val,
677 straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_timing_generator_v.c | 154 field = get_reg_field_value(value, CRTCV_STATUS, CRTC_V_BLANK);
168 h1 = get_reg_field_value(
173 v1 = get_reg_field_value(
180 h2 = get_reg_field_value(
185 v2 = get_reg_field_value(
612 uint32_t field = get_reg_field_value(
|
| amdgpu_dce110_timing_generator.c | 106 field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK);
205 struc_en = get_reg_field_value(
210 struc_stereo_sel_ovr = get_reg_field_value(
523 uint32_t field = get_reg_field_value(
547 position->horizontal_count = get_reg_field_value(
552 position->vertical_count = get_reg_field_value(
559 position->nominal_vcount = get_reg_field_value(
588 *v_blank_start = get_reg_field_value(value,
591 *v_blank_end = get_reg_field_value(value,
1291 check_point = get_reg_field_value(value_crtc_vtotal
[all...] |
| amdgpu_dce110_compressor.c | 128 if (get_reg_field_value(
281 if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
288 if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
291 if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
|
| amdgpu_dce110_opp_regamma_v.c | 79 if (get_reg_field_value(value,
82 get_reg_field_value(value,
|
| amdgpu_dce110_transform_v.c | 199 get_reg_field_value(value, SCLV_MODE, SCL_MODE),
204 get_reg_field_value(value, SCLV_MODE, SCL_PSCL_EN),
316 if (get_reg_field_value(
|
| amdgpu_dce110_opp_csc_v.c | 120 bool use_set_a = (get_reg_field_value(cntl_value,
561 use_set_a = get_reg_field_value(
|
| amdgpu_dce110_mem_input_v.c | 484 if (get_reg_field_value(value, UNP_GRPH_UPDATE,
|
| amdgpu_dce110_hw_sequencer.c | 157 chunk_int = get_reg_field_value(
162 chunk_mul = get_reg_field_value(
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_aux.c | 98 uint32_t field = get_reg_field_value(
111 uint32_t field = get_reg_field_value(
119 field = get_reg_field_value(value,
164 field = get_reg_field_value(
376 *returned_bytes = get_reg_field_value(value,
|
| amdgpu_dce_audio.c | 462 field = get_reg_field_value(value,
881 port_connectivity = get_reg_field_value(value,
|
| amdgpu_dce_link_encoder.c | 1382 get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services.h | 116 #define get_reg_field_value(reg_value, reg_name, reg_field)\ macro
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/ |
| amdgpu_irq_service_dce110.c | 54 uint32_t current_status = get_reg_field_value(value,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/ |
| amdgpu_irq_service_dce120.c | 54 get_reg_field_value(
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/ |
| amdgpu_irq_service_dce80.c | 54 get_reg_field_value(
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/ |
| amdgpu_irq_service_dcn10.c | 135 get_reg_field_value(
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/ |
| amdgpu_irq_service_dcn20.c | 135 get_reg_field_value(
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/ |
| amdgpu_irq_service_dcn21.c | 136 get_reg_field_value(
|
