1 /* $NetBSD: if_gfe.c,v 1.63 2025/10/04 04:44:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.63 2025/10/04 04:44:20 thorpej Exp $"); 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/bus.h> 51 #include <sys/callout.h> 52 #include <sys/device.h> 53 #include <sys/errno.h> 54 #include <sys/ioctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/mutex.h> 57 #include <sys/socket.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_ether.h> 62 #include <net/if_media.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/if_inarp.h> 67 #endif 68 #include <net/bpf.h> 69 #include <sys/rndsource.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 74 #include <dev/marvell/gtreg.h> 75 #include <dev/marvell/gtvar.h> 76 #include <dev/marvell/gtethreg.h> 77 #include <dev/marvell/if_gfevar.h> 78 #include <dev/marvell/marvellreg.h> 79 #include <dev/marvell/marvellvar.h> 80 81 #include <prop/proplib.h> 82 83 #include "locators.h" 84 85 86 #define GE_READ(sc, reg) \ 87 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg)) 88 #define GE_WRITE(sc, reg, v) \ 89 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (v)) 90 91 #define GE_DEBUG 92 #if 0 93 #define GE_NOHASH 94 #define GE_NORX 95 #endif 96 97 #ifdef GE_DEBUG 98 #define GE_DPRINTF(sc, a) \ 99 do { \ 100 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 101 printf a; \ 102 } while (0 /* CONSTCOND */) 103 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 104 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 105 #else 106 #define GE_DPRINTF(sc, a) do { } while (0) 107 #define GE_FUNC_ENTER(sc, func) do { } while (0) 108 #define GE_FUNC_EXIT(sc, str) do { } while (0) 109 #endif 110 enum gfe_whack_op { 111 GE_WHACK_START, GE_WHACK_RESTART, 112 GE_WHACK_CHANGE, GE_WHACK_STOP 113 }; 114 115 enum gfe_hash_op { 116 GE_HASH_ADD, GE_HASH_REMOVE, 117 }; 118 119 #if 1 120 #define htogt32(a) htobe32(a) 121 #define gt32toh(a) be32toh(a) 122 #else 123 #define htogt32(a) htole32(a) 124 #define gt32toh(a) le32toh(a) 125 #endif 126 127 #define GE_RXDSYNC(sc, rxq, n, ops) \ 128 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 129 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 130 (ops)) 131 #define GE_RXDPRESYNC(sc, rxq, n) \ 132 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE) 133 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 134 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE) 135 136 #define GE_TXDSYNC(sc, txq, n, ops) \ 137 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 138 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 139 (ops)) 140 #define GE_TXDPRESYNC(sc, txq, n) \ 141 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE) 142 #define GE_TXDPOSTSYNC(sc, txq, n) \ 143 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE) 144 145 #define STATIC 146 147 148 STATIC int gfec_match(device_t, cfdata_t, void *); 149 STATIC void gfec_attach(device_t, device_t, void *); 150 151 STATIC int gfec_print(void *, const char *); 152 STATIC int gfec_search(device_t, cfdata_t, const int *, void *); 153 154 STATIC int gfec_enet_phy(device_t, int); 155 STATIC int gfec_mii_read(device_t, int, int, uint16_t *); 156 STATIC int gfec_mii_write(device_t, int, int, uint16_t); 157 STATIC void gfec_mii_statchg(struct ifnet *); 158 159 STATIC int gfe_match(device_t, cfdata_t, void *); 160 STATIC void gfe_attach(device_t, device_t, void *); 161 162 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 163 size_t, int); 164 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 165 166 STATIC int gfe_ifioctl(struct ifnet *, u_long, void *); 167 STATIC void gfe_ifstart(struct ifnet *); 168 STATIC void gfe_ifwatchdog(struct ifnet *); 169 170 STATIC void gfe_tick(void *arg); 171 172 STATIC void gfe_tx_restart(void *); 173 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 174 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 175 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 176 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 177 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 178 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 179 180 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 181 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 182 STATIC int gfe_rx_prime(struct gfe_softc *); 183 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 184 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 185 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 186 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 187 188 STATIC int gfe_intr(void *); 189 190 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 191 192 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 193 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 194 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 195 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 196 u_long); 197 STATIC int gfe_hash_fill(struct gfe_softc *); 198 STATIC int gfe_hash_alloc(struct gfe_softc *); 199 200 201 CFATTACH_DECL_NEW(gfec, sizeof(struct gfec_softc), 202 gfec_match, gfec_attach, NULL, NULL); 203 CFATTACH_DECL_NEW(gfe, sizeof(struct gfe_softc), 204 gfe_match, gfe_attach, NULL, NULL); 205 206 207 /* ARGSUSED */ 208 int 209 gfec_match(device_t parent, cfdata_t cf, void *aux) 210 { 211 struct marvell_attach_args *mva = aux; 212 213 if (strcmp(mva->mva_name, cf->cf_name) != 0) 214 return 0; 215 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 216 return 0; 217 218 mva->mva_size = ETHC_SIZE; 219 return 1; 220 } 221 222 /* ARGSUSED */ 223 void 224 gfec_attach(device_t parent, device_t self, void *aux) 225 { 226 struct gfec_softc *sc = device_private(self); 227 struct marvell_attach_args *mva = aux, gfea; 228 static int gfe_irqs[] = { 32, 33, 34 }; 229 int i; 230 231 aprint_naive("\n"); 232 aprint_normal(": Ethernet Controller\n"); 233 234 sc->sc_dev = self; 235 sc->sc_iot = mva->mva_iot; 236 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 237 mva->mva_size, &sc->sc_ioh)) { 238 aprint_error_dev(self, "Cannot map registers\n"); 239 return; 240 } 241 242 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 243 244 for (i = 0; i < ETH_NUM; i++) { 245 gfea.mva_name = "gfe"; 246 gfea.mva_model = mva->mva_model; 247 gfea.mva_iot = sc->sc_iot; 248 gfea.mva_ioh = sc->sc_ioh; 249 gfea.mva_unit = i; 250 gfea.mva_dmat = mva->mva_dmat; 251 gfea.mva_irq = gfe_irqs[i]; 252 config_found(sc->sc_dev, &gfea, gfec_print, 253 CFARGS(.submatch = gfec_search)); 254 } 255 } 256 257 int 258 gfec_print(void *aux, const char *pnp) 259 { 260 struct marvell_attach_args *gfea = aux; 261 262 if (pnp) 263 aprint_normal("%s at %s port %d", 264 gfea->mva_name, pnp, gfea->mva_unit); 265 else { 266 if (gfea->mva_unit != GFECCF_PORT_DEFAULT) 267 aprint_normal(" port %d", gfea->mva_unit); 268 if (gfea->mva_irq != GFECCF_IRQ_DEFAULT) 269 aprint_normal(" irq %d", gfea->mva_irq); 270 } 271 return UNCONF; 272 } 273 274 /* ARGSUSED */ 275 int 276 gfec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 277 { 278 struct marvell_attach_args *gfea = aux; 279 280 if (cf->cf_loc[GFECCF_PORT] == gfea->mva_unit && 281 cf->cf_loc[GFECCF_IRQ] != GFECCF_IRQ_DEFAULT) 282 gfea->mva_irq = cf->cf_loc[GFECCF_IRQ]; 283 284 return config_match(parent, cf, aux); 285 } 286 287 int 288 gfec_enet_phy(device_t dev, int unit) 289 { 290 struct gfec_softc *sc = device_private(dev); 291 uint32_t epar; 292 293 epar = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ETH_EPAR); 294 return ETH_EPAR_PhyAD_GET(epar, unit); 295 } 296 297 int 298 gfec_mii_read(device_t dev, int phy, int reg, uint16_t *val) 299 { 300 struct gfec_softc *csc = device_private(device_parent(dev)); 301 uint32_t data; 302 int count = 10000; 303 304 mutex_enter(&csc->sc_mtx); 305 306 do { 307 DELAY(10); 308 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 309 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 310 311 if (count == 0) { 312 aprint_error_dev(dev, 313 "mii read for phy %d reg %d busied out\n", phy, reg); 314 mutex_exit(&csc->sc_mtx); 315 return ETIMEDOUT; 316 } 317 318 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 319 ETH_ESMIR_READ(phy, reg)); 320 321 count = 10000; 322 do { 323 DELAY(10); 324 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 325 } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0); 326 327 mutex_exit(&csc->sc_mtx); 328 329 if (count == 0) { 330 aprint_error_dev(dev, 331 "mii read for phy %d reg %d timed out\n", phy, reg); 332 return ETIMEDOUT; 333 } 334 #if defined(GTMIIDEBUG) 335 aprint_normal_dev(dev, "mii_read(%d, %d): %#x data %#x\n", 336 phy, reg, data, ETH_ESMIR_Value_GET(data)); 337 #endif 338 *val = ETH_ESMIR_Value_GET(data); 339 return 0; 340 } 341 342 int 343 gfec_mii_write(device_t dev, int phy, int reg, uint16_t value) 344 { 345 struct gfec_softc *csc = device_private(device_parent(dev)); 346 uint32_t data; 347 int count = 10000; 348 349 mutex_enter(&csc->sc_mtx); 350 351 do { 352 DELAY(10); 353 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 354 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 355 356 if (count == 0) { 357 aprint_error_dev(dev, 358 "mii write for phy %d reg %d busied out (busy)\n", 359 phy, reg); 360 mutex_exit(&csc->sc_mtx); 361 return ETIMEDOUT; 362 } 363 364 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 365 ETH_ESMIR_WRITE(phy, reg, value)); 366 367 count = 10000; 368 do { 369 DELAY(10); 370 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 371 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 372 373 mutex_exit(&csc->sc_mtx); 374 375 if (count == 0) { 376 aprint_error_dev(dev, 377 "mii write for phy %d reg %d timed out\n", phy, reg); 378 return ETIMEDOUT; 379 } 380 #if defined(GTMIIDEBUG) 381 aprint_normal_dev(dev, "mii_write(%d, %d, %#hx)\n", phy, reg, value); 382 #endif 383 return 0; 384 } 385 386 void 387 gfec_mii_statchg(struct ifnet *ifp) 388 { 389 /* struct gfe_softc *sc = ifp->if_softc; */ 390 /* do nothing? */ 391 } 392 393 /* ARGSUSED */ 394 int 395 gfe_match(device_t parent, cfdata_t cf, void *aux) 396 { 397 398 return 1; 399 } 400 401 /* ARGSUSED */ 402 void 403 gfe_attach(device_t parent, device_t self, void *aux) 404 { 405 struct marvell_attach_args *mva = aux; 406 struct gfe_softc * const sc = device_private(self); 407 struct ifnet * const ifp = &sc->sc_ec.ec_if; 408 struct mii_data * const mii = &sc->sc_mii; 409 uint32_t sdcr; 410 int phyaddr, error; 411 uint8_t enaddr[ETHER_ADDR_LEN] = { 0 }; 412 413 aprint_naive("\n"); 414 aprint_normal(": Ethernet Controller\n"); 415 416 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 417 mva->mva_offset, mva->mva_size, &sc->sc_memh)) { 418 aprint_error_dev(self, "failed to map registers\n"); 419 return; 420 } 421 sc->sc_dev = self; 422 sc->sc_memt = mva->mva_iot; 423 sc->sc_dmat = mva->mva_dmat; 424 sc->sc_macno = (mva->mva_offset == ETH_BASE(0)) ? 0 : 425 ((mva->mva_offset == ETH_BASE(1)) ? 1 : 2); 426 427 callout_init(&sc->sc_co, 0); 428 429 phyaddr = gfec_enet_phy(parent, sc->sc_macno); 430 431 if (! ether_getaddr(sc->sc_dev, enaddr)) { 432 aprint_error_dev(self, "unable to get mac-address\n"); 433 return; 434 } 435 436 sc->sc_pcr = GE_READ(sc, ETH_EPCR); 437 sc->sc_pcxr = GE_READ(sc, ETH_EPCXR); 438 sc->sc_intrmask = GE_READ(sc, ETH_EIMR) | ETH_IR_MIIPhySTC; 439 440 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 441 442 #if defined(DEBUG) 443 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 444 #endif 445 446 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 447 if (device_cfdata(self)->cf_flags & 1) { 448 aprint_normal_dev(self, "phy %d (rmii)\n", phyaddr); 449 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 450 } else { 451 aprint_normal_dev(self, "phy %d (mii)\n", phyaddr); 452 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 453 } 454 if (device_cfdata(self)->cf_flags & 2) 455 sc->sc_flags |= GE_NOFREE; 456 /* Set Max Frame Length is 1536 */ 457 sc->sc_pcxr &= ~ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_MASK); 458 sc->sc_pcxr |= ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_1536); 459 sc->sc_max_frame_length = 1536; 460 461 if (sc->sc_pcr & ETH_EPCR_EN) { 462 int tries = 1000; 463 /* 464 * Abort transmitter and receiver and wait for them to quiese 465 */ 466 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR | ETH_ESDCMR_AT); 467 do { 468 delay(100); 469 if (tries-- <= 0) { 470 aprint_error_dev(self, "Abort TX/RX failed\n"); 471 break; 472 } 473 } while (GE_READ(sc, ETH_ESDCMR) & 474 (ETH_ESDCMR_AR | ETH_ESDCMR_AT)); 475 } 476 477 sc->sc_pcr &= 478 ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 479 480 #if defined(DEBUG) 481 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 482 #endif 483 484 /* 485 * Now turn off the GT. If it didn't quiese, too ***ing bad. 486 */ 487 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 488 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 489 sdcr = GE_READ(sc, ETH_ESDCR); 490 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 491 sdcr |= ETH_ESDCR_RIFB; 492 GE_WRITE(sc, ETH_ESDCR, sdcr); 493 494 mii->mii_ifp = ifp; 495 mii->mii_readreg = gfec_mii_read; 496 mii->mii_writereg = gfec_mii_write; 497 mii->mii_statchg = gfec_mii_statchg; 498 499 sc->sc_ec.ec_mii = mii; 500 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 501 502 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 503 MII_OFFSET_ANY, MIIF_NOISOLATE); 504 if (LIST_FIRST(&mii->mii_phys) == NULL) { 505 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 506 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 507 } else 508 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 509 510 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 511 ifp->if_softc = sc; 512 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 513 #if 0 514 ifp->if_flags |= IFF_DEBUG; 515 #endif 516 ifp->if_ioctl = gfe_ifioctl; 517 ifp->if_start = gfe_ifstart; 518 ifp->if_watchdog = gfe_ifwatchdog; 519 520 if (sc->sc_flags & GE_NOFREE) { 521 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 522 if (!error) 523 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 524 if (!error) 525 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 526 if (!error) 527 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 528 if (!error) 529 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 530 if (!error) 531 error = gfe_hash_alloc(sc); 532 if (error) 533 aprint_error_dev(self, 534 "failed to allocate resources: %d\n", error); 535 } 536 537 if_attach(ifp); 538 ether_ifattach(ifp, enaddr); 539 bpf_attach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 540 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), RND_TYPE_NET, 541 RND_FLAG_DEFAULT); 542 marvell_intr_establish(mva->mva_irq, IPL_NET, gfe_intr, sc); 543 } 544 545 int 546 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 547 size_t size, int flags) 548 { 549 int error = 0; 550 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 551 552 KASSERT(gdm->gdm_kva == NULL); 553 gdm->gdm_size = size; 554 gdm->gdm_maxsegs = maxsegs; 555 556 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 557 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 558 BUS_DMA_NOWAIT); 559 if (error) 560 goto fail; 561 562 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 563 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 564 if (error) 565 goto fail; 566 567 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 568 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW |BUS_DMA_NOWAIT, &gdm->gdm_map); 569 if (error) 570 goto fail; 571 572 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 573 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 574 if (error) 575 goto fail; 576 577 /* invalidate from cache */ 578 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 579 BUS_DMASYNC_PREREAD); 580 fail: 581 if (error) { 582 gfe_dmamem_free(sc, gdm); 583 GE_DPRINTF(sc, (":err=%d", error)); 584 } 585 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 586 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 587 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 588 GE_FUNC_EXIT(sc, ""); 589 return error; 590 } 591 592 void 593 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 594 { 595 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 596 if (gdm->gdm_map) 597 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 598 if (gdm->gdm_kva) 599 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 600 if (gdm->gdm_nsegs > 0) 601 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 602 gdm->gdm_map = NULL; 603 gdm->gdm_kva = NULL; 604 gdm->gdm_nsegs = 0; 605 GE_FUNC_EXIT(sc, ""); 606 } 607 608 int 609 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 610 { 611 struct gfe_softc * const sc = ifp->if_softc; 612 struct ifreq *ifr = (struct ifreq *) data; 613 struct ifaddr *ifa = (struct ifaddr *) data; 614 int s, error = 0; 615 616 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 617 s = splnet(); 618 619 switch (cmd) { 620 case SIOCINITIFADDR: 621 ifp->if_flags |= IFF_UP; 622 error = gfe_whack(sc, GE_WHACK_START); 623 switch (ifa->ifa_addr->sa_family) { 624 #ifdef INET 625 case AF_INET: 626 if (error == 0) 627 arp_ifinit(ifp, ifa); 628 break; 629 #endif 630 default: 631 break; 632 } 633 break; 634 635 case SIOCSIFFLAGS: 636 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 637 break; 638 /* XXX re-use ether_ioctl() */ 639 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 640 case IFF_UP | IFF_RUNNING:/* active->active, update */ 641 error = gfe_whack(sc, GE_WHACK_CHANGE); 642 break; 643 case IFF_RUNNING: /* not up, so we stop */ 644 error = gfe_whack(sc, GE_WHACK_STOP); 645 break; 646 case IFF_UP: /* not running, so we start */ 647 error = gfe_whack(sc, GE_WHACK_START); 648 break; 649 case 0: /* idle->idle: do nothing */ 650 break; 651 } 652 break; 653 654 case SIOCSIFMTU: 655 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 656 error = EINVAL; 657 break; 658 } 659 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 660 error = 0; 661 break; 662 663 default: 664 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 665 if (ifp->if_flags & IFF_RUNNING) 666 error = gfe_whack(sc, GE_WHACK_CHANGE); 667 else 668 error = 0; 669 } 670 break; 671 } 672 splx(s); 673 GE_FUNC_EXIT(sc, ""); 674 return error; 675 } 676 677 void 678 gfe_ifstart(struct ifnet *ifp) 679 { 680 struct gfe_softc * const sc = ifp->if_softc; 681 struct mbuf *m; 682 683 GE_FUNC_ENTER(sc, "gfe_ifstart"); 684 685 if ((ifp->if_flags & IFF_RUNNING) == 0) { 686 GE_FUNC_EXIT(sc, "$"); 687 return; 688 } 689 690 for (;;) { 691 IF_POLL(&ifp->if_snd, m); 692 if (m == NULL) { 693 ifp->if_flags &= ~IFF_OACTIVE; 694 GE_FUNC_EXIT(sc, ""); 695 return; 696 } 697 698 /* 699 * No space in the pending queue? try later. 700 */ 701 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 702 break; 703 704 IF_DEQUEUE(&ifp->if_snd, m); 705 706 /* 707 * Try to enqueue a mbuf to the device. If that fails, we 708 * can always try to map the next mbuf. 709 */ 710 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 711 GE_DPRINTF(sc, (">")); 712 #ifndef GE_NOTX 713 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 714 #endif 715 } 716 717 /* 718 * Attempt to queue the mbuf for send failed. 719 */ 720 ifp->if_flags |= IFF_OACTIVE; 721 GE_FUNC_EXIT(sc, "%%"); 722 } 723 724 void 725 gfe_ifwatchdog(struct ifnet *ifp) 726 { 727 struct gfe_softc * const sc = ifp->if_softc; 728 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 729 730 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 731 aprint_error_dev(sc->sc_dev, "device timeout"); 732 if (ifp->if_flags & IFF_RUNNING) { 733 uint32_t curtxdnum; 734 735 curtxdnum = (GE_READ(sc, txq->txq_ectdp) - 736 txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 737 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 738 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 739 aprint_error(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 740 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 741 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 742 GE_READ(sc, ETH_EICR)); 743 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 744 GE_TXDPRESYNC(sc, txq, curtxdnum); 745 } 746 aprint_error("\n"); 747 if_statinc(ifp, if_oerrors); 748 (void) gfe_whack(sc, GE_WHACK_RESTART); 749 GE_FUNC_EXIT(sc, ""); 750 } 751 752 int 753 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 754 { 755 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 756 int error; 757 758 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 759 GE_DPRINTF(sc, ("(%d)", rxprio)); 760 761 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 762 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 763 if (error) { 764 GE_FUNC_EXIT(sc, "!!"); 765 return error; 766 } 767 768 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 769 GE_RXBUF_MEMSIZE, 0); 770 if (error) { 771 GE_FUNC_EXIT(sc, "!!!"); 772 return error; 773 } 774 GE_FUNC_EXIT(sc, ""); 775 return error; 776 } 777 778 int 779 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 780 { 781 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 782 volatile struct gt_eth_desc *rxd; 783 const bus_dma_segment_t *ds; 784 int idx; 785 bus_addr_t nxtaddr; 786 bus_size_t boff; 787 788 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 789 GE_DPRINTF(sc, ("(%d)", rxprio)); 790 791 if ((sc->sc_flags & GE_NOFREE) == 0) { 792 int error = gfe_rx_rxqalloc(sc, rxprio); 793 if (error) { 794 GE_FUNC_EXIT(sc, "!"); 795 return error; 796 } 797 } else { 798 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 799 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 800 } 801 802 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 803 804 rxq->rxq_descs = 805 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 806 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 807 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 808 rxq->rxq_fi = 0; 809 rxq->rxq_active = GE_RXDESC_MAX; 810 boff = 0; 811 ds = rxq->rxq_buf_mem.gdm_map->dm_segs; 812 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 813 for (idx = 0, rxd = rxq->rxq_descs; idx < GE_RXDESC_MAX; 814 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 815 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 816 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 817 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 818 /* 819 * update the nxtptr to point to the next txd. 820 */ 821 if (idx == GE_RXDESC_MAX - 1) 822 nxtaddr = rxq->rxq_desc_busaddr; 823 rxd->ed_nxtptr = htogt32(nxtaddr); 824 boff += GE_RXBUF_SIZE; 825 if (boff == ds->ds_len) { 826 ds++; 827 boff = 0; 828 } 829 } 830 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 831 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 832 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 833 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 834 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 835 BUS_DMASYNC_PREREAD); 836 837 rxq->rxq_intrbits = ETH_IR_RxBuffer | ETH_IR_RxError; 838 switch (rxprio) { 839 case GE_RXPRIO_HI: 840 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3 | ETH_IR_RxError_3; 841 rxq->rxq_efrdp = ETH_EFRDP3; 842 rxq->rxq_ecrdp = ETH_ECRDP3; 843 break; 844 case GE_RXPRIO_MEDHI: 845 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2 | ETH_IR_RxError_2; 846 rxq->rxq_efrdp = ETH_EFRDP2; 847 rxq->rxq_ecrdp = ETH_ECRDP2; 848 break; 849 case GE_RXPRIO_MEDLO: 850 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1 | ETH_IR_RxError_1; 851 rxq->rxq_efrdp = ETH_EFRDP1; 852 rxq->rxq_ecrdp = ETH_ECRDP1; 853 break; 854 case GE_RXPRIO_LO: 855 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0 | ETH_IR_RxError_0; 856 rxq->rxq_efrdp = ETH_EFRDP0; 857 rxq->rxq_ecrdp = ETH_ECRDP0; 858 break; 859 } 860 GE_FUNC_EXIT(sc, ""); 861 return 0; 862 } 863 864 void 865 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 866 { 867 struct ifnet * const ifp = &sc->sc_ec.ec_if; 868 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 869 struct mbuf *m = rxq->rxq_curpkt; 870 871 GE_FUNC_ENTER(sc, "gfe_rx_get"); 872 GE_DPRINTF(sc, ("(%d)", rxprio)); 873 874 while (rxq->rxq_active > 0) { 875 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 876 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 877 const struct ether_header *eh; 878 unsigned int cmdsts; 879 size_t buflen; 880 881 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 882 cmdsts = gt32toh(rxd->ed_cmdsts); 883 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 884 rxq->rxq_cmdsts = cmdsts; 885 /* 886 * Sometimes the GE "forgets" to reset the ownership bit. 887 * But if the length has been rewritten, the packet is ours 888 * so pretend the O bit is set. 889 */ 890 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 891 if ((cmdsts & RX_CMD_O) && buflen == 0) { 892 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 893 break; 894 } 895 896 /* 897 * If this is not a single buffer packet with no errors 898 * or for some reason it's bigger than our frame size, 899 * ignore it and go to the next packet. 900 */ 901 if ((cmdsts & (RX_CMD_F | RX_CMD_L | RX_STS_ES)) != 902 (RX_CMD_F | RX_CMD_L) || 903 (buflen > sc->sc_max_frame_length)) { 904 GE_DPRINTF(sc, ("!")); 905 --rxq->rxq_active; 906 if_statinc(ifp, if_ipackets); 907 if_statinc(ifp, if_ierrors); 908 goto give_it_back; 909 } 910 911 /* CRC is included with the packet; trim it off. */ 912 buflen -= ETHER_CRC_LEN; 913 914 if (m == NULL) { 915 MGETHDR(m, M_DONTWAIT, MT_DATA); 916 if (m == NULL) { 917 GE_DPRINTF(sc, ("?")); 918 break; 919 } 920 } 921 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 922 MCLGET(m, M_DONTWAIT); 923 if ((m->m_flags & M_EXT) == 0) { 924 GE_DPRINTF(sc, ("?")); 925 break; 926 } 927 } 928 m->m_data += 2; 929 m->m_len = 0; 930 m->m_pkthdr.len = 0; 931 m_set_rcvif(m, ifp); 932 rxq->rxq_cmdsts = cmdsts; 933 --rxq->rxq_active; 934 935 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 936 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 937 938 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 939 memcpy(m->m_data + m->m_len, rxb->rxb_data, buflen); 940 m->m_len = buflen; 941 m->m_pkthdr.len = buflen; 942 943 eh = (const struct ether_header *) m->m_data; 944 if ((ifp->if_flags & IFF_PROMISC) || 945 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 946 (rxq->rxq_cmdsts & RX_STS_HE) || 947 (eh->ether_dhost[0] & 1) != 0 || 948 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 949 ETHER_ADDR_LEN) == 0) { 950 if_percpuq_enqueue(ifp->if_percpuq, m); 951 m = NULL; 952 GE_DPRINTF(sc, (">")); 953 } else { 954 m->m_len = 0; 955 m->m_pkthdr.len = 0; 956 GE_DPRINTF(sc, ("+")); 957 } 958 rxq->rxq_cmdsts = 0; 959 960 give_it_back: 961 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 962 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 963 #if 0 964 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 965 rxq->rxq_fi, 966 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 967 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 968 #endif 969 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 970 if (++rxq->rxq_fi == GE_RXDESC_MAX) 971 rxq->rxq_fi = 0; 972 rxq->rxq_active++; 973 } 974 rxq->rxq_curpkt = m; 975 GE_FUNC_EXIT(sc, ""); 976 } 977 978 uint32_t 979 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 980 { 981 struct ifnet * const ifp = &sc->sc_ec.ec_if; 982 struct gfe_rxqueue *rxq; 983 uint32_t rxbits; 984 #define RXPRIO_DECODER 0xffffaa50 985 GE_FUNC_ENTER(sc, "gfe_rx_process"); 986 987 rxbits = ETH_IR_RxBuffer_GET(cause); 988 while (rxbits) { 989 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 990 GE_DPRINTF(sc, ("%1x", rxbits)); 991 rxbits &= ~(1 << rxprio); 992 gfe_rx_get(sc, rxprio); 993 } 994 995 rxbits = ETH_IR_RxError_GET(cause); 996 while (rxbits) { 997 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 998 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 999 int idx; 1000 rxbits &= ~(1 << rxprio); 1001 rxq = &sc->sc_rxq[rxprio]; 1002 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 1003 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 1004 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 1005 sc->sc_tickflags |= GE_TICK_RX_RESTART; 1006 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 1007 } 1008 if_statinc(ifp, if_ierrors); 1009 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 1010 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi)); 1011 memset(masks, 0, sizeof(masks)); 1012 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1013 0, rxq->rxq_desc_mem.gdm_size, 1014 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1015 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 1016 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 1017 1018 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 1019 masks[idx/32] |= 1 << (idx & 31); 1020 } 1021 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1022 0, rxq->rxq_desc_mem.gdm_size, 1023 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1024 #if defined(DEBUG) 1025 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 1026 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi, 1027 rxq->rxq_cmdsts, masks[0], masks[1]); 1028 #endif 1029 } 1030 if ((intrmask & ETH_IR_RxBits) == 0) 1031 intrmask &= ~(ETH_IR_RxBuffer | ETH_IR_RxError); 1032 1033 GE_FUNC_EXIT(sc, ""); 1034 return intrmask; 1035 } 1036 1037 int 1038 gfe_rx_prime(struct gfe_softc *sc) 1039 { 1040 struct gfe_rxqueue *rxq; 1041 int error; 1042 1043 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 1044 1045 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 1046 if (error) 1047 goto bail; 1048 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1049 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1050 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1051 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1052 } 1053 sc->sc_intrmask |= rxq->rxq_intrbits; 1054 1055 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 1056 if (error) 1057 goto bail; 1058 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1059 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1060 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1061 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1062 sc->sc_intrmask |= rxq->rxq_intrbits; 1063 } 1064 1065 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 1066 if (error) 1067 goto bail; 1068 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1069 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1070 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1071 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1072 sc->sc_intrmask |= rxq->rxq_intrbits; 1073 } 1074 1075 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 1076 if (error) 1077 goto bail; 1078 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1079 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1080 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1081 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1082 sc->sc_intrmask |= rxq->rxq_intrbits; 1083 } 1084 1085 bail: 1086 GE_FUNC_EXIT(sc, ""); 1087 return error; 1088 } 1089 1090 void 1091 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 1092 { 1093 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 1094 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 1095 if (rxq == NULL) { 1096 GE_FUNC_EXIT(sc, ""); 1097 return; 1098 } 1099 1100 m_freem(rxq->rxq_curpkt); 1101 if ((sc->sc_flags & GE_NOFREE) == 0) { 1102 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 1103 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 1104 } 1105 GE_FUNC_EXIT(sc, ""); 1106 } 1107 1108 void 1109 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1110 { 1111 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 1112 sc->sc_flags &= ~GE_RXACTIVE; 1113 sc->sc_idlemask &= ~(ETH_IR_RxBits | ETH_IR_RxBuffer | ETH_IR_RxError); 1114 sc->sc_intrmask &= ~(ETH_IR_RxBits | ETH_IR_RxBuffer | ETH_IR_RxError); 1115 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1116 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR); 1117 do { 1118 delay(10); 1119 } while (GE_READ(sc, ETH_ESDCMR) & ETH_ESDCMR_AR); 1120 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 1121 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 1122 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 1123 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 1124 GE_FUNC_EXIT(sc, ""); 1125 } 1126 1127 void 1128 gfe_tick(void *arg) 1129 { 1130 struct gfe_softc * const sc = arg; 1131 uint32_t intrmask; 1132 unsigned int tickflags; 1133 int s; 1134 1135 GE_FUNC_ENTER(sc, "gfe_tick"); 1136 1137 s = splnet(); 1138 1139 tickflags = sc->sc_tickflags; 1140 sc->sc_tickflags = 0; 1141 intrmask = sc->sc_intrmask; 1142 if (tickflags & GE_TICK_TX_IFSTART) 1143 gfe_ifstart(&sc->sc_ec.ec_if); 1144 if (tickflags & GE_TICK_RX_RESTART) { 1145 intrmask |= sc->sc_idlemask; 1146 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3 | ETH_IR_RxError_3)) { 1147 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1148 rxq->rxq_fi = 0; 1149 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1150 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1151 } 1152 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2 | ETH_IR_RxError_2)) { 1153 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1154 rxq->rxq_fi = 0; 1155 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1156 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1157 } 1158 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1 | ETH_IR_RxError_1)) { 1159 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1160 rxq->rxq_fi = 0; 1161 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1162 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1163 } 1164 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0 | ETH_IR_RxError_0)) { 1165 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1166 rxq->rxq_fi = 0; 1167 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1168 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1169 } 1170 sc->sc_idlemask = 0; 1171 } 1172 if (intrmask != sc->sc_intrmask) { 1173 sc->sc_intrmask = intrmask; 1174 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1175 } 1176 gfe_intr(sc); 1177 splx(s); 1178 1179 GE_FUNC_EXIT(sc, ""); 1180 } 1181 1182 int 1183 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1184 { 1185 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1186 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1187 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1188 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1189 uint32_t intrmask = sc->sc_intrmask; 1190 size_t buflen; 1191 struct mbuf *m; 1192 1193 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1194 1195 /* 1196 * Anything in the pending queue to enqueue? if not, punt. Likewise 1197 * if the txq is not yet created. 1198 * otherwise grab its dmamap. 1199 */ 1200 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1201 GE_FUNC_EXIT(sc, "-"); 1202 return 0; 1203 } 1204 1205 /* 1206 * Have we [over]consumed our limit of descriptors? 1207 * Do we have enough free descriptors? 1208 */ 1209 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1210 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1211 uint32_t cmdsts; 1212 size_t pktlen; 1213 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1214 cmdsts = gt32toh(txd2->ed_cmdsts); 1215 if (cmdsts & TX_CMD_O) { 1216 int nextin; 1217 /* 1218 * Sometime the Discovery forgets to update the 1219 * last descriptor. See if we own the descriptor 1220 * after it (since we know we've turned that to 1221 * the discovery and if we owned it, the Discovery 1222 * gave it back). If we do, we know the Discovery 1223 * gave back this one but forgot to mark it as ours. 1224 */ 1225 nextin = txq->txq_fi + 1; 1226 if (nextin == GE_TXDESC_MAX) 1227 nextin = 0; 1228 GE_TXDPOSTSYNC(sc, txq, nextin); 1229 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1230 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1231 GE_TXDPRESYNC(sc, txq, nextin); 1232 GE_FUNC_EXIT(sc, "@"); 1233 return 0; 1234 } 1235 #ifdef DEBUG 1236 printf("%s: txenqueue: transmitter resynced at %d\n", 1237 device_xname(sc->sc_dev), txq->txq_fi); 1238 #endif 1239 } 1240 if (++txq->txq_fi == GE_TXDESC_MAX) 1241 txq->txq_fi = 0; 1242 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1243 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1244 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1245 txq->txq_nactive--; 1246 1247 /* statistics */ 1248 if_statinc(ifp, if_opackets); 1249 if (cmdsts & TX_STS_ES) 1250 if_statinc(ifp, if_oerrors); 1251 GE_DPRINTF(sc, ("%%")); 1252 } 1253 1254 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1255 1256 /* 1257 * If this packet would wrap around the end of the buffer, reset back 1258 * to the beginning. 1259 */ 1260 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1261 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1262 txq->txq_outptr = 0; 1263 } 1264 1265 /* 1266 * Make sure the output packet doesn't run over the beginning of 1267 * what we've already given the GT. 1268 */ 1269 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1270 txq->txq_outptr + buflen > txq->txq_inptr) { 1271 intrmask |= txq->txq_intrbits & 1272 (ETH_IR_TxBufferHigh | ETH_IR_TxBufferLow); 1273 if (sc->sc_intrmask != intrmask) { 1274 sc->sc_intrmask = intrmask; 1275 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1276 } 1277 GE_FUNC_EXIT(sc, "#"); 1278 return 0; 1279 } 1280 1281 /* 1282 * The end-of-list descriptor we put on last time is the starting point 1283 * for this packet. The GT is supposed to terminate list processing on 1284 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1285 * must terminate the list. 1286 */ 1287 intrmask = sc->sc_intrmask; 1288 1289 m_copydata(m, 0, m->m_pkthdr.len, 1290 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1291 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1292 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1293 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1294 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1295 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1296 1297 /* 1298 * Request a buffer interrupt every 2/3 of the way thru the transmit 1299 * buffer. 1300 */ 1301 txq->txq_ei_gapcount += buflen; 1302 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1303 txd->ed_cmdsts = htogt32(TX_CMD_FIRST |TX_CMD_LAST |TX_CMD_EI); 1304 txq->txq_ei_gapcount = 0; 1305 } else { 1306 txd->ed_cmdsts = htogt32(TX_CMD_FIRST | TX_CMD_LAST); 1307 } 1308 #if 0 1309 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1310 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1311 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1312 #endif 1313 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1314 1315 txq->txq_outptr += buflen; 1316 /* 1317 * Tell the SDMA engine to "Fetch!" 1318 */ 1319 GE_WRITE(sc, ETH_ESDCMR, 1320 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH | ETH_ESDCMR_TXDL)); 1321 1322 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1323 1324 /* 1325 * Update the last out appropriately. 1326 */ 1327 txq->txq_nactive++; 1328 if (++txq->txq_lo == GE_TXDESC_MAX) 1329 txq->txq_lo = 0; 1330 1331 /* 1332 * Move mbuf from the pending queue to the snd queue. 1333 */ 1334 IF_DEQUEUE(&txq->txq_pendq, m); 1335 bpf_mtap(ifp, m, BPF_D_OUT); 1336 m_freem(m); 1337 ifp->if_flags &= ~IFF_OACTIVE; 1338 1339 /* 1340 * Since we have put an item into the packet queue, we now want 1341 * an interrupt when the transmit queue finishes processing the 1342 * list. But only update the mask if needs changing. 1343 */ 1344 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh | ETH_IR_TxEndLow); 1345 if (sc->sc_intrmask != intrmask) { 1346 sc->sc_intrmask = intrmask; 1347 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1348 } 1349 if (ifp->if_timer == 0) 1350 ifp->if_timer = 5; 1351 GE_FUNC_EXIT(sc, "*"); 1352 return 1; 1353 } 1354 1355 uint32_t 1356 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1357 { 1358 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1359 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1360 1361 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1362 1363 if (txq == NULL) { 1364 GE_FUNC_EXIT(sc, ""); 1365 return intrmask; 1366 } 1367 1368 while (txq->txq_nactive > 0) { 1369 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1370 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1371 uint32_t cmdsts; 1372 size_t pktlen; 1373 1374 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1375 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1376 int nextin; 1377 1378 if (txq->txq_nactive == 1) { 1379 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1380 GE_FUNC_EXIT(sc, ""); 1381 return intrmask; 1382 } 1383 /* 1384 * Sometimes the Discovery forgets to update the 1385 * ownership bit in the descriptor. See if we own the 1386 * descriptor after it (since we know we've turned 1387 * that to the Discovery and if we own it now then the 1388 * Discovery gave it back). If we do, we know the 1389 * Discovery gave back this one but forgot to mark it 1390 * as ours. 1391 */ 1392 nextin = txq->txq_fi + 1; 1393 if (nextin == GE_TXDESC_MAX) 1394 nextin = 0; 1395 GE_TXDPOSTSYNC(sc, txq, nextin); 1396 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1397 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1398 GE_TXDPRESYNC(sc, txq, nextin); 1399 GE_FUNC_EXIT(sc, ""); 1400 return intrmask; 1401 } 1402 #ifdef DEBUG 1403 printf("%s: txdone: transmitter resynced at %d\n", 1404 device_xname(sc->sc_dev), txq->txq_fi); 1405 #endif 1406 } 1407 #if 0 1408 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1409 txq->txq_lo, 1410 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1411 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1412 #endif 1413 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1414 if (++txq->txq_fi == GE_TXDESC_MAX) 1415 txq->txq_fi = 0; 1416 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1417 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1418 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1419 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1420 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1421 1422 /* statistics */ 1423 if_statinc(ifp, if_opackets); 1424 if (cmdsts & TX_STS_ES) 1425 if_statinc(ifp, if_oerrors); 1426 1427 /* txd->ed_bufptr = 0; */ 1428 1429 ifp->if_timer = 5; 1430 --txq->txq_nactive; 1431 } 1432 if (txq->txq_nactive != 0) 1433 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1434 device_xname(sc->sc_dev), txprio, txq->txq_nactive); 1435 ifp->if_timer = 0; 1436 intrmask &= 1437 ~(txq->txq_intrbits & (ETH_IR_TxEndHigh | ETH_IR_TxEndLow)); 1438 intrmask &= 1439 ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh | ETH_IR_TxBufferLow)); 1440 GE_FUNC_EXIT(sc, ""); 1441 return intrmask; 1442 } 1443 1444 int 1445 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1446 { 1447 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1448 int error; 1449 1450 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1451 1452 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1453 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1454 if (error) { 1455 GE_FUNC_EXIT(sc, ""); 1456 return error; 1457 } 1458 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1459 if (error) { 1460 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1461 GE_FUNC_EXIT(sc, ""); 1462 return error; 1463 } 1464 GE_FUNC_EXIT(sc, ""); 1465 return 0; 1466 } 1467 1468 int 1469 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1470 { 1471 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1472 volatile struct gt_eth_desc *txd; 1473 unsigned int i; 1474 bus_addr_t addr; 1475 1476 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1477 1478 sc->sc_intrmask &= 1479 ~(ETH_IR_TxEndHigh | 1480 ETH_IR_TxBufferHigh | 1481 ETH_IR_TxEndLow | 1482 ETH_IR_TxBufferLow); 1483 1484 if (sc->sc_flags & GE_NOFREE) { 1485 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1486 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1487 } else { 1488 int error = gfe_tx_txqalloc(sc, txprio); 1489 if (error) { 1490 GE_FUNC_EXIT(sc, "!"); 1491 return error; 1492 } 1493 } 1494 1495 txq->txq_descs = 1496 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1497 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1498 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1499 1500 txq->txq_pendq.ifq_maxlen = 10; 1501 txq->txq_ei_gapcount = 0; 1502 txq->txq_nactive = 0; 1503 txq->txq_fi = 0; 1504 txq->txq_lo = 0; 1505 txq->txq_inptr = GE_TXBUF_SIZE; 1506 txq->txq_outptr = 0; 1507 for (i = 0, txd = txq->txq_descs, 1508 addr = txq->txq_desc_busaddr + sizeof(*txd); 1509 i < GE_TXDESC_MAX - 1; i++, txd++, addr += sizeof(*txd)) { 1510 /* 1511 * update the nxtptr to point to the next txd. 1512 */ 1513 txd->ed_cmdsts = 0; 1514 txd->ed_nxtptr = htogt32(addr); 1515 } 1516 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1517 htogt32(txq->txq_desc_busaddr); 1518 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1519 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1520 1521 switch (txprio) { 1522 case GE_TXPRIO_HI: 1523 txq->txq_intrbits = ETH_IR_TxEndHigh | ETH_IR_TxBufferHigh; 1524 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1525 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1526 txq->txq_ectdp = ETH_ECTDP1; 1527 GE_WRITE(sc, ETH_ECTDP1, txq->txq_desc_busaddr); 1528 break; 1529 1530 case GE_TXPRIO_LO: 1531 txq->txq_intrbits = ETH_IR_TxEndLow | ETH_IR_TxBufferLow; 1532 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1533 txq->txq_epsrbits = ETH_EPSR_TxLow; 1534 txq->txq_ectdp = ETH_ECTDP0; 1535 GE_WRITE(sc, ETH_ECTDP0, txq->txq_desc_busaddr); 1536 break; 1537 1538 case GE_TXPRIO_NONE: 1539 break; 1540 } 1541 #if 0 1542 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1543 GE_WRITE(sc->sc_dev, txq->txq_ectdp, txq->txq_desc_busaddr); 1544 GE_DPRINTF(sc, (")")); 1545 #endif 1546 1547 /* 1548 * If we are restarting, there may be packets in the pending queue 1549 * waiting to be enqueued. Try enqueuing packets from both priority 1550 * queues until the pending queue is empty or there no room for them 1551 * on the device. 1552 */ 1553 while (gfe_tx_enqueue(sc, txprio)) 1554 continue; 1555 1556 GE_FUNC_EXIT(sc, ""); 1557 return 0; 1558 } 1559 1560 void 1561 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1562 { 1563 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1564 1565 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1566 if (txq == NULL) { 1567 GE_FUNC_EXIT(sc, ""); 1568 return; 1569 } 1570 1571 if (!flush) { 1572 GE_FUNC_EXIT(sc, ""); 1573 return; 1574 } 1575 1576 if ((sc->sc_flags & GE_NOFREE) == 0) { 1577 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1578 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1579 } 1580 GE_FUNC_EXIT(sc, "-F"); 1581 } 1582 1583 void 1584 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1585 { 1586 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1587 1588 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_STDH | ETH_ESDCMR_STDL); 1589 1590 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1591 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1592 sc->sc_intrmask &= 1593 ~(ETH_IR_TxEndHigh | 1594 ETH_IR_TxBufferHigh | 1595 ETH_IR_TxEndLow | 1596 ETH_IR_TxBufferLow); 1597 1598 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1599 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1600 1601 sc->sc_ec.ec_if.if_timer = 0; 1602 GE_FUNC_EXIT(sc, ""); 1603 } 1604 1605 int 1606 gfe_intr(void *arg) 1607 { 1608 struct gfe_softc * const sc = arg; 1609 uint32_t cause; 1610 uint32_t intrmask = sc->sc_intrmask; 1611 int claim = 0; 1612 int cnt; 1613 1614 GE_FUNC_ENTER(sc, "gfe_intr"); 1615 1616 for (cnt = 0; cnt < 4; cnt++) { 1617 if (sc->sc_intrmask != intrmask) { 1618 sc->sc_intrmask = intrmask; 1619 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1620 } 1621 cause = GE_READ(sc, ETH_EICR); 1622 cause &= sc->sc_intrmask; 1623 GE_DPRINTF(sc, (".%#x", cause)); 1624 if (cause == 0) 1625 break; 1626 1627 claim = 1; 1628 1629 GE_WRITE(sc, ETH_EICR, ~cause); 1630 #ifndef GE_NORX 1631 if (cause & (ETH_IR_RxBuffer | ETH_IR_RxError)) 1632 intrmask = gfe_rx_process(sc, cause, intrmask); 1633 #endif 1634 1635 #ifndef GE_NOTX 1636 if (cause & (ETH_IR_TxBufferHigh | ETH_IR_TxEndHigh)) 1637 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1638 if (cause & (ETH_IR_TxBufferLow | ETH_IR_TxEndLow)) 1639 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1640 #endif 1641 if (cause & ETH_IR_MIIPhySTC) { 1642 sc->sc_flags |= GE_PHYSTSCHG; 1643 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1644 } 1645 } 1646 1647 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1648 continue; 1649 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1650 continue; 1651 1652 GE_FUNC_EXIT(sc, ""); 1653 return claim; 1654 } 1655 1656 int 1657 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1658 { 1659 int error = 0; 1660 GE_FUNC_ENTER(sc, "gfe_whack"); 1661 1662 switch (op) { 1663 case GE_WHACK_RESTART: 1664 #ifndef GE_NOTX 1665 gfe_tx_stop(sc, op); 1666 #endif 1667 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1668 /* FALLTHROUGH */ 1669 case GE_WHACK_START: 1670 #ifndef GE_NOHASH 1671 if (error == 0 && sc->sc_hashtable == NULL) { 1672 error = gfe_hash_alloc(sc); 1673 if (error) 1674 break; 1675 } 1676 if (op != GE_WHACK_RESTART) 1677 gfe_hash_fill(sc); 1678 #endif 1679 #ifndef GE_NORX 1680 if (op != GE_WHACK_RESTART) { 1681 error = gfe_rx_prime(sc); 1682 if (error) 1683 break; 1684 } 1685 #endif 1686 #ifndef GE_NOTX 1687 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1688 if (error) 1689 break; 1690 #endif 1691 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1692 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1693 GE_WRITE(sc, ETH_EPCXR, sc->sc_pcxr); 1694 GE_WRITE(sc, ETH_EICR, 0); 1695 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1696 #ifndef GE_NOHASH 1697 GE_WRITE(sc, ETH_EHTPR, 1698 sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1699 #endif 1700 #ifndef GE_NORX 1701 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_ERD); 1702 sc->sc_flags |= GE_RXACTIVE; 1703 #endif 1704 /* FALLTHROUGH */ 1705 case GE_WHACK_CHANGE: 1706 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1707 GE_READ(sc, ETH_EPCR), GE_READ(sc, ETH_EIMR))); 1708 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1709 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1710 gfe_ifstart(&sc->sc_ec.ec_if); 1711 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1712 GE_READ(sc, ETH_ECTDP0), GE_READ(sc, ETH_ECTDP1))); 1713 GE_FUNC_EXIT(sc, ""); 1714 return error; 1715 case GE_WHACK_STOP: 1716 break; 1717 } 1718 1719 #ifdef GE_DEBUG 1720 if (error) 1721 GE_DPRINTF(sc, (" failed: %d\n", error)); 1722 #endif 1723 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1724 GE_WRITE(sc, ETH_EIMR, 0); 1725 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1726 #ifndef GE_NOTX 1727 gfe_tx_stop(sc, GE_WHACK_STOP); 1728 #endif 1729 #ifndef GE_NORX 1730 gfe_rx_stop(sc, GE_WHACK_STOP); 1731 #endif 1732 #ifndef GE_NOHASH 1733 if ((sc->sc_flags & GE_NOFREE) == 0) { 1734 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1735 sc->sc_hashtable = NULL; 1736 } 1737 #endif 1738 1739 GE_FUNC_EXIT(sc, ""); 1740 return error; 1741 } 1742 1743 int 1744 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1745 { 1746 uint32_t w0, add0, add1; 1747 uint32_t result; 1748 1749 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1750 add0 = ((uint32_t) eaddr[5] << 0) | 1751 ((uint32_t) eaddr[4] << 8) | 1752 ((uint32_t) eaddr[3] << 16); 1753 1754 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1755 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1756 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1757 1758 add1 = ((uint32_t) eaddr[2] << 0) | 1759 ((uint32_t) eaddr[1] << 8) | 1760 ((uint32_t) eaddr[0] << 16); 1761 1762 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1763 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1764 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1765 1766 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1767 /* 1768 * hashResult is the 15 bits Hash entry address. 1769 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1770 * MAC address, by nibble swapping in every byte (i.e MAC address 1771 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1772 */ 1773 1774 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1775 /* 1776 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1777 * 1778 * hashFunc0 calculates the hashResult in the following manner: 1779 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1780 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1781 */ 1782 result = (add0 & 3) | ((add0 >> 6) & ~3); 1783 result ^= (add0 >> 15) ^ (add1 >> 0); 1784 result &= 0x1ff; 1785 /* 1786 * hashResult[14:9] = ethernetADD[7:2] 1787 */ 1788 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1789 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1790 } else { 1791 #define TRIBITFLIP 073516240 /* yes its in octal */ 1792 /* 1793 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1794 * 1795 * hashFunc1 calculates the hashResult in the following manner: 1796 * hashResult[08:00] = ethernetADD[06:14] 1797 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1798 */ 1799 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1800 /* 1801 * Now bitswap those 9 bits 1802 */ 1803 result = 0; 1804 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1805 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1806 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1807 1808 /* 1809 * hashResult[14:09] = ethernetADD[00:05] 1810 */ 1811 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1812 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1813 GE_DPRINTF(sc, ("1(%#x)", result)); 1814 } 1815 GE_FUNC_EXIT(sc, ""); 1816 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1817 } 1818 1819 int 1820 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1821 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1822 { 1823 uint64_t he; 1824 uint64_t *maybe_he_p = NULL; 1825 int limit; 1826 int hash; 1827 int maybe_hash = 0; 1828 1829 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1830 1831 hash = gfe_hash_compute(sc, eaddr); 1832 1833 if (sc->sc_hashtable == NULL) { 1834 panic("%s:%d: hashtable == NULL!", device_xname(sc->sc_dev), 1835 __LINE__); 1836 } 1837 1838 /* 1839 * Assume we are going to insert so create the hash entry we 1840 * are going to insert. We also use it to match entries we 1841 * will be removing. 1842 */ 1843 he = ((uint64_t) eaddr[5] << 43) | 1844 ((uint64_t) eaddr[4] << 35) | 1845 ((uint64_t) eaddr[3] << 27) | 1846 ((uint64_t) eaddr[2] << 19) | 1847 ((uint64_t) eaddr[1] << 11) | 1848 ((uint64_t) eaddr[0] << 3) | 1849 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1850 1851 /* 1852 * The GT will search upto 12 entries for a hit, so we must mimic that. 1853 */ 1854 hash &= sc->sc_hashmask / sizeof(he); 1855 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1856 /* 1857 * Does the GT wrap at the end, stop at the, or overrun the 1858 * end? Assume it wraps for now. Stash a copy of the 1859 * current hash entry. 1860 */ 1861 uint64_t *he_p = &sc->sc_hashtable[hash]; 1862 uint64_t thishe = *he_p; 1863 1864 /* 1865 * If the hash entry isn't valid, that break the chain. And 1866 * this entry a good candidate for reuse. 1867 */ 1868 if ((thishe & HSH_V) == 0) { 1869 maybe_he_p = he_p; 1870 break; 1871 } 1872 1873 /* 1874 * If the hash entry has the same address we are looking for 1875 * then ... if we are removing and the skip bit is set, its 1876 * already been removed. if are adding and the skip bit is 1877 * clear, then its already added. In either return EBUSY 1878 * indicating the op has already been done. Otherwise flip 1879 * the skip bit and return 0. 1880 */ 1881 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1882 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1883 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1884 return EBUSY; 1885 *he_p = thishe ^ HSH_S; 1886 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1887 hash * sizeof(he), sizeof(he), 1888 BUS_DMASYNC_PREWRITE); 1889 GE_FUNC_EXIT(sc, "^"); 1890 return 0; 1891 } 1892 1893 /* 1894 * If we haven't found a slot for the entry and this entry 1895 * is currently being skipped, return this entry. 1896 */ 1897 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1898 maybe_he_p = he_p; 1899 maybe_hash = hash; 1900 } 1901 1902 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1903 } 1904 1905 /* 1906 * If we got here, then there was no entry to remove. 1907 */ 1908 if (op == GE_HASH_REMOVE) { 1909 GE_FUNC_EXIT(sc, "?"); 1910 return ENOENT; 1911 } 1912 1913 /* 1914 * If we couldn't find a slot, return an error. 1915 */ 1916 if (maybe_he_p == NULL) { 1917 GE_FUNC_EXIT(sc, "!"); 1918 return ENOSPC; 1919 } 1920 1921 /* Update the entry. 1922 */ 1923 *maybe_he_p = he; 1924 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1925 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1926 GE_FUNC_EXIT(sc, "+"); 1927 return 0; 1928 } 1929 1930 int 1931 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, 1932 u_long cmd) 1933 { 1934 struct gfe_softc *sc = ec->ec_if.if_softc; 1935 int error; 1936 enum gfe_hash_op op; 1937 enum gfe_rxprio prio; 1938 1939 GE_FUNC_ENTER(sc, "hash_multichg"); 1940 /* 1941 * Is this a wildcard entry? If so and its being removed, recompute. 1942 */ 1943 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1944 if (cmd == SIOCDELMULTI) { 1945 GE_FUNC_EXIT(sc, ""); 1946 return ENETRESET; 1947 } 1948 1949 /* 1950 * Switch in 1951 */ 1952 sc->sc_flags |= GE_ALLMULTI; 1953 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1954 sc->sc_pcr |= ETH_EPCR_PM; 1955 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1956 GE_FUNC_EXIT(sc, ""); 1957 return 0; 1958 } 1959 GE_FUNC_EXIT(sc, ""); 1960 return ENETRESET; 1961 } 1962 1963 prio = GE_RXPRIO_MEDLO; 1964 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1965 1966 if (sc->sc_hashtable == NULL) { 1967 GE_FUNC_EXIT(sc, ""); 1968 return 0; 1969 } 1970 1971 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1972 if (error == EBUSY) { 1973 aprint_error_dev(sc->sc_dev, "multichg: tried to %s %s again\n", 1974 cmd == SIOCDELMULTI ? "remove" : "add", 1975 ether_sprintf(enm->enm_addrlo)); 1976 GE_FUNC_EXIT(sc, ""); 1977 return 0; 1978 } 1979 1980 if (error == ENOENT) { 1981 aprint_error_dev(sc->sc_dev, 1982 "multichg: failed to remove %s: not in table\n", 1983 ether_sprintf(enm->enm_addrlo)); 1984 GE_FUNC_EXIT(sc, ""); 1985 return 0; 1986 } 1987 1988 if (error == ENOSPC) { 1989 aprint_error_dev(sc->sc_dev, "multichg:" 1990 " failed to add %s: no space; regenerating table\n", 1991 ether_sprintf(enm->enm_addrlo)); 1992 GE_FUNC_EXIT(sc, ""); 1993 return ENETRESET; 1994 } 1995 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1996 device_xname(sc->sc_dev), 1997 cmd == SIOCDELMULTI ? "remove" : "add", 1998 ether_sprintf(enm->enm_addrlo))); 1999 GE_FUNC_EXIT(sc, ""); 2000 return 0; 2001 } 2002 2003 int 2004 gfe_hash_fill(struct gfe_softc *sc) 2005 { 2006 struct ethercom *ec = &sc->sc_ec; 2007 struct ether_multistep step; 2008 struct ether_multi *enm; 2009 int error; 2010 2011 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 2012 2013 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 2014 CLLADDR(ec->ec_if.if_sadl)); 2015 if (error) { 2016 GE_FUNC_EXIT(sc, "!"); 2017 return error; 2018 } 2019 2020 sc->sc_flags &= ~GE_ALLMULTI; 2021 if ((ec->ec_if.if_flags & IFF_PROMISC) == 0) 2022 sc->sc_pcr &= ~ETH_EPCR_PM; 2023 ETHER_LOCK(ec); 2024 ETHER_FIRST_MULTI(step, ec, enm); 2025 while (enm != NULL) { 2026 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2027 sc->sc_flags |= GE_ALLMULTI; 2028 sc->sc_pcr |= ETH_EPCR_PM; 2029 } else { 2030 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 2031 GE_RXPRIO_MEDLO, enm->enm_addrlo); 2032 if (error == ENOSPC) 2033 break; 2034 } 2035 ETHER_NEXT_MULTI(step, enm); 2036 } 2037 ETHER_UNLOCK(ec); 2038 2039 GE_FUNC_EXIT(sc, ""); 2040 return error; 2041 } 2042 2043 int 2044 gfe_hash_alloc(struct gfe_softc *sc) 2045 { 2046 int error; 2047 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 2048 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 2049 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 2050 BUS_DMA_NOCACHE); 2051 if (error) { 2052 aprint_error_dev(sc->sc_dev, 2053 "failed to allocate %d bytes for hash table: %d\n", 2054 sc->sc_hashmask + 1, error); 2055 GE_FUNC_EXIT(sc, ""); 2056 return error; 2057 } 2058 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 2059 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 2060 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 2061 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 2062 GE_FUNC_EXIT(sc, ""); 2063 return 0; 2064 } 2065
Indexes created Tue Oct 07 21:09:53 GMT 2025