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    Searched refs:gfx8 (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_debug.c 135 "plane_state->tiling_info.gfx8.num_banks = %d;\n"
136 "plane_state->tiling_info.gfx8.bank_width = %d;\n"
137 "plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
138 "plane_state->tiling_info.gfx8.bank_height = %d;\n"
139 "plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
140 "plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
141 "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
142 "plane_state->tiling_info.gfx8.tile_split = %d;\n"
143 "plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
144 "plane_state->tiling_info.gfx8.tile_mode = %d;\n
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_mem_input.c 108 switch (tiling_info->gfx8.array_mode) {
377 if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
379 GRPH_NUM_BANKS, info->gfx8.num_banks,
380 GRPH_BANK_WIDTH, info->gfx8.bank_width,
381 GRPH_BANK_HEIGHT, info->gfx8.bank_height,
382 GRPH_MACRO_TILE_ASPECT, info->gfx8.tile_aspect,
383 GRPH_TILE_SPLIT, info->gfx8.tile_split,
384 GRPH_MICRO_TILE_MODE, info->gfx8.tile_mode,
385 GRPH_PIPE_CONFIG, info->gfx8.pipe_config,
386 GRPH_ARRAY_MODE, info->gfx8.array_mode
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_mem_input_v.c 177 set_reg_field_value(value, info->gfx8.num_banks,
180 set_reg_field_value(value, info->gfx8.bank_width,
183 set_reg_field_value(value, info->gfx8.bank_height,
186 set_reg_field_value(value, info->gfx8.tile_aspect,
189 set_reg_field_value(value, info->gfx8.tile_split,
192 set_reg_field_value(value, info->gfx8.tile_mode,
195 set_reg_field_value(value, info->gfx8.pipe_config,
198 set_reg_field_value(value, info->gfx8.array_mode,
214 set_reg_field_value(value, info->gfx8.bank_width_c,
217 set_reg_field_value(value, info->gfx8.bank_height_c
    [all...]
amdgpu_dce110_hw_sequencer.c 1837 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_hw_types.h 344 } gfx8; member in union:dc_tiling_info
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c 3261 /* Fill GFX8 params */
3272 tiling_info->gfx8.num_banks = num_banks;
3273 tiling_info->gfx8.array_mode =
3275 tiling_info->gfx8.tile_split = tile_split;
3276 tiling_info->gfx8.bank_width = bankw;
3277 tiling_info->gfx8.bank_height = bankh;
3278 tiling_info->gfx8.tile_aspect = mtaspect;
3279 tiling_info->gfx8.tile_mode =
3283 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
3286 tiling_info->gfx8.pipe_config
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