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    Searched refs:gfx9 (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_mem_input.c 363 if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */
365 GRPH_SW_MODE, info->gfx9.swizzle,
366 GRPH_NUM_BANKS, log_2(info->gfx9.num_banks),
367 GRPH_NUM_SHADER_ENGINES, log_2(info->gfx9.num_shader_engines),
368 GRPH_NUM_PIPES, log_2(info->gfx9.num_pipes),
370 GRPH_SE_ENABLE, info->gfx9.shaderEnable);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hubp.c 154 NUM_PIPES, log_2(info->gfx9.num_pipes),
155 NUM_BANKS, log_2(info->gfx9.num_banks),
156 PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
157 NUM_SE, log_2(info->gfx9.num_shader_engines),
158 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
159 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
162 SW_MODE, info->gfx9.swizzle,
163 META_LINEAR, info->gfx9.meta_linear,
164 RB_ALIGNED, info->gfx9.rb_aligned,
165 PIPE_ALIGNED, info->gfx9.pipe_aligned)
    [all...]
amdgpu_dcn10_resource.c 1255 plane_state->tiling_info.gfx9.swizzle = swizzle;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_debug.c 174 SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
175 plane_state->tiling_info.gfx9.swizzle);
260 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
261 update->plane_info->tiling_info.gfx9.swizzle);
amdgpu_dc.c 1570 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
amdgpu_dc_resource.c 2118 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_hw_types.h 360 } gfx9; member in union:dc_tiling_info
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hubp.c 318 NUM_PIPES, log_2(info->gfx9.num_pipes),
319 PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
320 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
323 SW_MODE, info->gfx9.swizzle,
amdgpu_dcn20_resource.c 2163 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2164 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
3049 plane_state->tiling_info.gfx9.swizzle = swizzle;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c 3173 input.swizzle_mode = tiling_info->gfx9.swizzle;
3297 /* Fill GFX9 params */
3298 tiling_info->gfx9.num_pipes =
3300 tiling_info->gfx9.num_banks =
3302 tiling_info->gfx9.pipe_interleave =
3304 tiling_info->gfx9.num_shader_engines =
3306 tiling_info->gfx9.max_compressed_frags =
3308 tiling_info->gfx9.num_rb_per_se =
3310 tiling_info->gfx9.swizzle =
3312 tiling_info->gfx9.shaderEnable = 1
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 336 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;
345 input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
984 pipe->plane_state->tiling_info.gfx9.swizzle);

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