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    Searched refs:gfxclk (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_smu_v11_0.c 534 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
549 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
amdgpu_vega20_ppt.c 158 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
747 /* gfxclk */
754 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
759 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
1212 pr_err("Failed to set soft %s gfxclk !\n",
1489 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1826 "GFXCLK",
1907 case 0: /* Gfxclk */
2103 /* gfxclk */
2585 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100
    [all...]
amdgpu_arcturus_ppt.c 138 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
446 /* gfxclk */
452 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
457 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
759 pr_err("Failed to set soft %s gfxclk !\n",
1091 * But this is available for gfxclk/uclk/socclk.
1169 /* gfxclk */
1211 /* gfxclk */
1405 "GFXCLK",
1468 case 0: /* Gfxclk */
    [all...]
amdgpu_smu.c 298 clock_limit = smu->smu_table.boot_values.gfxclk;
1083 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1188 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
amdgpu_smu.h 214 uint32_t gfxclk; member in struct:smu_bios_boot_up_values
hwmgr.h 519 uint32_t gfxclk; member in struct:phm_clock_and_voltage_limits
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega10_processpptables.c 840 " GFXCLK Dpm Levels!"
870 limits->gfxclk = le32_to_cpu(limit_table->entries[0].ulGFXCLKLimit);

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