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    Searched refs:gmbus (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
edid.c 136 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
165 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
213 i2c_edid->gmbus.total_byte_count =
217 /* vgpu gmbus only support EDID */
222 "vgpu%d: unsupported gmbus slave addr(0x%x)\n"
223 " gmbus operations will be ignored.\n",
231 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
238 * if a GMBUS cycle is generated, the GMBUS is
249 * visible in gmbus interface
    [all...]
edid.h 70 * States of GMBUS
72 * GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS
74 * not considered here. Below describes the usage of GMBUS registers that are
100 * are invisible to GMBUS MMIO interface. So no definitions
129 * GMBUS and AUX_CH sequences cannot interleave.
139 struct intel_vgpu_i2c_gmbus gmbus; member in struct:intel_vgpu_i2c_edid
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_gmbus.c 53 /* Map gmbus pin pairs to names and registers. */
621 * The gmbus controller can combine a 1 or 2 byte write with another read/write
708 /* Generate a STOP condition on the bus. Note that gmbus can't generata
710 * unconditionally generate the STOP condition with an additional gmbus
714 /* Mark the GMBUS interface as disabled after waiting for idle.
719 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
737 * from retrying. So return -ENXIO only when gmbus properly quiescents -
743 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
749 * of resetting the GMBUS controller and so clearing the
756 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n"
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_drv.h 950 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; member in struct:drm_i915_private
952 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
957 * Base address of where the gmbus and gpio blocks are located (either

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