| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
| nouveau_nvkm_engine_gr_gv100.c | 33 gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm)
37 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80)));
38 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80)));
45 nvkm_error(subdev, "GPC%i/TPC%i/SM%d trap: "
47 gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : "");
49 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000);
50 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr);
54 gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
56 gv100_gr_trap_sm(gr, gpc, tpc, 0);
57 gv100_gr_trap_sm(gr, gpc, tpc, 1)
[all...] |
| nouveau_nvkm_engine_gr_ctxgp102.c | 57 int gpc, ppc, b, n = 0; local in function:gp102_grctx_generate_attrib
59 for (gpc = 0; gpc < gr->gpc_nr; gpc++)
60 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max;
73 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
74 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
75 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]
[all...] |
| nouveau_nvkm_engine_gr_ctxgm200.c | 60 const u8 gpc = gr->sm[sm].gpc; local in function:gm200_grctx_generate_smid_config
62 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8);
63 gpcs[gpc] |= sm << (tpc * 8);
92 int gpc, ppc, i; local in function:gm200_grctx_generate_dist_skip_table
94 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
95 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
96 u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]
[all...] |
| nouveau_nvkm_engine_gr_ctxgp100.c | 61 int gpc, ppc, b, n = 0; local in function:gp100_grctx_generate_attrib
63 for (gpc = 0; gpc < gr->gpc_nr; gpc++)
64 size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max;
77 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
78 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
79 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]
109 const u8 gpc = gr->sm[sm].gpc; local in function:gp100_grctx_generate_smid_config
[all...] |
| nouveau_nvkm_engine_gr_tu102.c | 50 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 +
64 u8 bank[GPC_MAX] = {}, gpc, i, j; local in function:tu102_gr_init_zcull
75 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
76 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
77 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
78 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
80 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
|
| nouveau_nvkm_engine_gr_ctxgv100.c | 78 int gpc, ppc, b, n = 0; local in function:gv100_grctx_generate_attrib
80 for (gpc = 0; gpc < gr->gpc_nr; gpc++)
81 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max;
93 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
94 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
95 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]
[all...] |
| nouveau_nvkm_engine_gr_gf117.c | 136 u8 bank[GPC_MAX] = {}, gpc, i, j; local in function:gf117_gr_init_zcull
147 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
148 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
149 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
150 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
152 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
|
| nouveau_nvkm_engine_gr_gf100.c | 1181 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
1188 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;
1189 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));
1190 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));
1191 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));
1195 nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, "
1197 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16,
1199 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
1242 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
1246 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648))
1362 int rop, gpc; local in function:gf100_gr_trap_intr
1505 u32 gpc; local in function:gf100_gr_ctxctl_debug
1860 int tpc, gpc; local in function:gf100_gr_oneinit_sm_id
2112 int gpc, i, j; local in function:gf100_gr_init_num_tpc_per_gpc
2157 int gpc, tpc; local in function:gf100_gr_init_419cc0
2209 u8 bank[GPC_MAX] = {}, gpc, i, j; local in function:gf100_gr_init_zcull
2242 int gpc, tpc, rop; local in function:gf100_gr_init
[all...] |
| nouveau_nvkm_engine_gr_gp102.c | 94 u32 mask = 0, data, gpc; local in function:gp102_gr_init_swdx_pes_mask
96 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
97 data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f;
98 mask |= data << (gpc * 4);
|
| nouveau_nvkm_engine_gr_ctxtu102.c | 39 tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
42 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
43 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
|
| nouveau_nvkm_engine_gr_ctxgf117.c | 262 int gpc, ppc; local in function:gf117_grctx_generate_attrib
269 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
270 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
271 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc];
272 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc];
274 const u32 o = PPC_UNIT(gpc, ppc, 0);
275 if (!(gr->ppc_mask[gpc] & (1 << ppc)))
279 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]
[all...] |
| nouveau_nvkm_engine_gr_gk104.c | 423 int gpc, ppc; local in function:gk104_gr_init_ppc_exceptions
425 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
426 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
427 if (!(gr->ppc_mask[gpc] & (1 << ppc)))
429 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
|
| nouveau_nvkm_engine_gr_ctxgf100.c | 1077 int gpc, tpc; local in function:gf100_grctx_generate_attrib
1084 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
1085 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
1086 const u32 o = TPC_UNIT(gpc, tpc, 0x0520);
1111 data |= gr->sm[sm++].gpc << (j * 8);
1280 int i, gpc; local in function:gf100_grctx_generate_alpha_beta_tables
1292 for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++)
[all...] |
| nouveau_nvkm_engine_gr_gp100.c | 77 gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
80 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
81 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105);
|
| nouveau_nvkm_engine_gr_ctxgm107.c | 926 int gpc, ppc, n = 0; local in function:gm107_grctx_generate_attrib
934 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
935 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
936 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
937 const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc];
939 const u32 o = PPC_UNIT(gpc, ppc, 0);
940 if (!(gr->ppc_mask[gpc] & (1 << ppc)))
944 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]
[all...] |
| gf100.h | 130 u8 gpc; member in struct:gf100_gr::__anon24812acc0308
176 void (*init_tex_hww_esr)(struct gf100_gr *, int gpc, int tpc);
177 void (*init_504430)(struct gf100_gr *, int gpc, int tpc);
178 void (*init_shader_exceptions)(struct gf100_gr *, int gpc, int tpc);
181 void (*trap_mp)(struct gf100_gr *, int gpc, int tpc);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvif/ |
| ifc00d.h | 39 __u8 gpc; member in struct:gp100_vmm_fault_cancel_v0
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/ |
| fault.h | 28 u8 gpc; member in struct:nvkm_fault_data
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/ingenic/ |
| cu1830-neo.dts | 29 gpios = <&gpc 17 GPIO_ACTIVE_HIGH>;
40 mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
41 miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
42 sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
43 cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
73 reset-gpios = <&gpc 13 GPIO_ACTIVE_LOW>;
153 interrupt-parent = <&gpc>;
|
| qi_lb60.dts | 114 col-gpios = <&gpc 10 0>, <&gpc 11 0>, <&gpc 12 0>, <&gpc 13 0>,
115 <&gpc 14 0>, <&gpc 15 0>, <&gpc 16 0>, <&gpc 17 0>;
186 sck-gpios = <&gpc 23 GPIO_ACTIVE_HIGH>;
187 mosi-gpios = <&gpc 22 GPIO_ACTIVE_HIGH>
[all...] |
| rs90.dts | 61 gpios = <&gpc 10 GPIO_ACTIVE_LOW>;
67 gpios = <&gpc 11 GPIO_ACTIVE_LOW>;
85 gpios = <&gpc 31 GPIO_ACTIVE_LOW>;
91 gpios = <&gpc 30 GPIO_ACTIVE_LOW>;
97 gpios = <&gpc 12 GPIO_ACTIVE_LOW>;
130 enable-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
238 cd-gpios = <&gpc 20 GPIO_ACTIVE_LOW>;
268 rb-gpios = <&gpc 27 GPIO_ACTIVE_HIGH>;
|
| cu1000-neo.dts | 56 interrupt-parent = <&gpc>;
73 reset-gpios = <&gpc 17 GPIO_ACTIVE_LOW>;
149 interrupt-parent = <&gpc>;
166 snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx6qp.dtsi | 84 &gpc {
85 compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
|
| s3c64xx-pinctrl.dtsi | 33 gpc: gpc { label
214 samsung,pins = "gpc-0", "gpc-1", "gpc-2";
220 samsung,pins = "gpc-3";
226 samsung,pins = "gpc-4", "gpc-5", "gpc-6";
232 samsung,pins = "gpc-7"
[all...] |
| s3c2416-pinctrl.dtsi | 25 gpc: gpc { label
|
