1 /* $NetBSD: intel_dsi_vbt.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Author: Shobhit Kumar <shobhit.kumar (at) intel.com> 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: intel_dsi_vbt.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $"); 31 32 #include <linux/gpio/consumer.h> 33 #include <linux/gpio/machine.h> 34 #include <linux/mfd/intel_soc_pmic.h> 35 #include <linux/pinctrl/consumer.h> 36 #include <linux/pinctrl/machine.h> 37 #include <linux/slab.h> 38 39 #include <asm/intel-mid.h> 40 #include <asm/unaligned.h> 41 42 #include <drm/drm_crtc.h> 43 #include <drm/drm_edid.h> 44 #include <drm/i915_drm.h> 45 46 #include <video/mipi_display.h> 47 48 #include "i915_drv.h" 49 #include "intel_display_types.h" 50 #include "intel_dsi.h" 51 #include "intel_sideband.h" 52 53 #define MIPI_TRANSFER_MODE_SHIFT 0 54 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 55 #define MIPI_PORT_SHIFT 3 56 57 /* base offsets for gpio pads */ 58 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 59 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 60 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 61 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 62 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 63 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 64 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 65 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 66 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 67 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 68 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 69 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 70 71 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 72 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 73 74 struct gpio_map { 75 u16 base_offset; 76 bool init; 77 }; 78 79 static struct gpio_map vlv_gpio_table[] = { 80 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 81 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 82 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 83 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 84 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 85 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 86 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 87 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 88 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 89 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 90 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 91 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 92 }; 93 94 struct i2c_adapter_lookup { 95 u16 slave_addr; 96 struct intel_dsi *intel_dsi; 97 acpi_handle dev_handle; 98 }; 99 100 #define CHV_GPIO_IDX_START_N 0 101 #define CHV_GPIO_IDX_START_E 73 102 #define CHV_GPIO_IDX_START_SW 100 103 #define CHV_GPIO_IDX_START_SE 198 104 105 #define CHV_VBT_MAX_PINS_PER_FMLY 15 106 107 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 108 #define CHV_GPIO_GPIOEN (1 << 15) 109 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 110 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 111 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 112 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 113 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 114 115 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 116 #define CHV_GPIO_CFGLOCK (1 << 31) 117 118 /* ICL DSI Display GPIO Pins */ 119 #define ICL_GPIO_DDSP_HPD_A 0 120 #define ICL_GPIO_L_VDDEN_1 1 121 #define ICL_GPIO_L_BKLTEN_1 2 122 #define ICL_GPIO_DDPA_CTRLCLK_1 3 123 #define ICL_GPIO_DDPA_CTRLDATA_1 4 124 #define ICL_GPIO_DDSP_HPD_B 5 125 #define ICL_GPIO_L_VDDEN_2 6 126 #define ICL_GPIO_L_BKLTEN_2 7 127 #define ICL_GPIO_DDPA_CTRLCLK_2 8 128 #define ICL_GPIO_DDPA_CTRLDATA_2 9 129 130 static inline enum port intel_dsi_seq_port_to_port(u8 port) 131 { 132 return port ? PORT_C : PORT_A; 133 } 134 135 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 136 const u8 *data) 137 { 138 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 139 struct mipi_dsi_device *dsi_device; 140 u8 type, flags, seq_port; 141 u16 len; 142 enum port port; 143 144 DRM_DEBUG_KMS("\n"); 145 146 flags = *data++; 147 type = *data++; 148 149 len = *((u16 *) data); 150 data += 2; 151 152 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 153 154 /* For DSI single link on Port A & C, the seq_port value which is 155 * parsed from Sequence Block#53 of VBT has been set to 0 156 * Now, read/write of packets for the DSI single link on Port A and 157 * Port C will based on the DVO port from VBT block 2. 158 */ 159 if (intel_dsi->ports == (1 << PORT_C)) 160 port = PORT_C; 161 else 162 port = intel_dsi_seq_port_to_port(seq_port); 163 164 dsi_device = intel_dsi->dsi_hosts[port]->device; 165 if (!dsi_device) { 166 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port)); 167 goto out; 168 } 169 170 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 171 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 172 else 173 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 174 175 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 176 177 switch (type) { 178 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 179 mipi_dsi_generic_write(dsi_device, NULL, 0); 180 break; 181 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 182 mipi_dsi_generic_write(dsi_device, data, 1); 183 break; 184 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 185 mipi_dsi_generic_write(dsi_device, data, 2); 186 break; 187 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 188 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 189 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 190 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); 191 break; 192 case MIPI_DSI_GENERIC_LONG_WRITE: 193 mipi_dsi_generic_write(dsi_device, data, len); 194 break; 195 case MIPI_DSI_DCS_SHORT_WRITE: 196 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 197 break; 198 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 199 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 200 break; 201 case MIPI_DSI_DCS_READ: 202 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); 203 break; 204 case MIPI_DSI_DCS_LONG_WRITE: 205 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 206 break; 207 } 208 209 if (INTEL_GEN(dev_priv) < 11) 210 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 211 212 out: 213 data += len; 214 215 return data; 216 } 217 218 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 219 { 220 u32 delay = *((const u32 *) data); 221 222 DRM_DEBUG_KMS("\n"); 223 224 usleep_range(delay, delay + 10); 225 data += 4; 226 227 return data; 228 } 229 230 static void vlv_exec_gpio(struct drm_i915_private *dev_priv, 231 u8 gpio_source, u8 gpio_index, bool value) 232 { 233 struct gpio_map *map; 234 u16 pconf0, padval; 235 u32 tmp; 236 u8 port; 237 238 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 239 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); 240 return; 241 } 242 243 map = &vlv_gpio_table[gpio_index]; 244 245 if (dev_priv->vbt.dsi.seq_version >= 3) { 246 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 247 port = IOSF_PORT_GPIO_NC; 248 } else { 249 if (gpio_source == 0) { 250 port = IOSF_PORT_GPIO_NC; 251 } else if (gpio_source == 1) { 252 DRM_DEBUG_KMS("SC gpio not supported\n"); 253 return; 254 } else { 255 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); 256 return; 257 } 258 } 259 260 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 261 padval = VLV_GPIO_PAD_VAL(map->base_offset); 262 263 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 264 if (!map->init) { 265 /* FIXME: remove constant below */ 266 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 267 map->init = true; 268 } 269 270 tmp = 0x4 | value; 271 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 272 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 273 } 274 275 static void chv_exec_gpio(struct drm_i915_private *dev_priv, 276 u8 gpio_source, u8 gpio_index, bool value) 277 { 278 u16 cfg0, cfg1; 279 u16 family_num; 280 u8 port; 281 282 if (dev_priv->vbt.dsi.seq_version >= 3) { 283 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 284 /* XXX: it's unclear whether 255->57 is part of SE. */ 285 gpio_index -= CHV_GPIO_IDX_START_SE; 286 port = CHV_IOSF_PORT_GPIO_SE; 287 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 288 gpio_index -= CHV_GPIO_IDX_START_SW; 289 port = CHV_IOSF_PORT_GPIO_SW; 290 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 291 gpio_index -= CHV_GPIO_IDX_START_E; 292 port = CHV_IOSF_PORT_GPIO_E; 293 } else { 294 port = CHV_IOSF_PORT_GPIO_N; 295 } 296 } else { 297 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 298 if (gpio_source != 0) { 299 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); 300 return; 301 } 302 303 if (gpio_index >= CHV_GPIO_IDX_START_E) { 304 DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n", 305 gpio_index); 306 return; 307 } 308 309 port = CHV_IOSF_PORT_GPIO_N; 310 } 311 312 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 313 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 314 315 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 316 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 317 318 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 319 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 320 vlv_iosf_sb_write(dev_priv, port, cfg0, 321 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 322 CHV_GPIO_GPIOTXSTATE(value)); 323 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 324 } 325 326 static void bxt_exec_gpio(struct drm_i915_private *dev_priv, 327 u8 gpio_source, u8 gpio_index, bool value) 328 { 329 /* XXX: this table is a quick ugly hack. */ 330 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 331 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 332 333 if (!gpio_desc) { 334 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 335 NULL, gpio_index, 336 value ? GPIOD_OUT_LOW : 337 GPIOD_OUT_HIGH); 338 339 if (IS_ERR_OR_NULL(gpio_desc)) { 340 DRM_ERROR("GPIO index %u request failed (%ld)\n", 341 gpio_index, PTR_ERR(gpio_desc)); 342 return; 343 } 344 345 bxt_gpio_table[gpio_index] = gpio_desc; 346 } 347 348 gpiod_set_value(gpio_desc, value); 349 } 350 351 static void icl_exec_gpio(struct drm_i915_private *dev_priv, 352 u8 gpio_source, u8 gpio_index, bool value) 353 { 354 DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n"); 355 } 356 357 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 358 { 359 struct drm_device *dev = intel_dsi->base.base.dev; 360 struct drm_i915_private *dev_priv = to_i915(dev); 361 u8 gpio_source, gpio_index = 0, gpio_number; 362 bool value; 363 364 DRM_DEBUG_KMS("\n"); 365 366 if (dev_priv->vbt.dsi.seq_version >= 3) 367 gpio_index = *data++; 368 369 gpio_number = *data++; 370 371 /* gpio source in sequence v2 only */ 372 if (dev_priv->vbt.dsi.seq_version == 2) 373 gpio_source = (*data >> 1) & 3; 374 else 375 gpio_source = 0; 376 377 /* pull up/down */ 378 value = *data++ & 1; 379 380 if (INTEL_GEN(dev_priv) >= 11) 381 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); 382 else if (IS_VALLEYVIEW(dev_priv)) 383 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 384 else if (IS_CHERRYVIEW(dev_priv)) 385 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 386 else 387 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value); 388 389 return data; 390 } 391 392 #ifdef CONFIG_ACPI 393 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 394 { 395 struct i2c_adapter_lookup *lookup = data; 396 struct intel_dsi *intel_dsi = lookup->intel_dsi; 397 struct acpi_resource_i2c_serialbus *sb; 398 struct i2c_adapter *adapter; 399 acpi_handle adapter_handle; 400 acpi_status status; 401 402 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 403 return 1; 404 405 if (lookup->slave_addr != sb->slave_address) 406 return 1; 407 408 status = acpi_get_handle(lookup->dev_handle, 409 sb->resource_source.string_ptr, 410 &adapter_handle); 411 if (ACPI_FAILURE(status)) 412 return 1; 413 414 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 415 if (adapter) 416 intel_dsi->i2c_bus_num = adapter->nr; 417 418 return 1; 419 } 420 421 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 422 const u16 slave_addr) 423 { 424 struct drm_device *drm_dev = intel_dsi->base.base.dev; 425 struct device *dev = &drm_dev->pdev->dev; 426 struct acpi_device *acpi_dev; 427 struct list_head resource_list; 428 struct i2c_adapter_lookup lookup; 429 430 acpi_dev = ACPI_COMPANION(dev); 431 if (acpi_dev) { 432 memset(&lookup, 0, sizeof(lookup)); 433 lookup.slave_addr = slave_addr; 434 lookup.intel_dsi = intel_dsi; 435 lookup.dev_handle = acpi_device_handle(acpi_dev); 436 437 INIT_LIST_HEAD(&resource_list); 438 acpi_dev_get_resources(acpi_dev, &resource_list, 439 i2c_adapter_lookup, 440 &lookup); 441 acpi_dev_free_resource_list(&resource_list); 442 } 443 } 444 #else 445 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 446 const u16 slave_addr) 447 { 448 } 449 #endif 450 451 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 452 { 453 struct drm_device *drm_dev = intel_dsi->base.base.dev; 454 struct device *dev = &drm_dev->pdev->dev; 455 struct i2c_adapter *adapter; 456 struct i2c_msg msg; 457 int ret; 458 u8 vbt_i2c_bus_num = *(data + 2); 459 u16 slave_addr = *(u16 *)(data + 3); 460 u8 reg_offset = *(data + 5); 461 u8 payload_size = *(data + 6); 462 u8 *payload_data; 463 464 if (intel_dsi->i2c_bus_num < 0) { 465 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 466 i2c_acpi_find_adapter(intel_dsi, slave_addr); 467 } 468 469 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 470 if (!adapter) { 471 DRM_DEV_ERROR(dev, "Cannot find a valid i2c bus for xfer\n"); 472 goto err_bus; 473 } 474 475 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 476 if (!payload_data) 477 goto err_alloc; 478 479 payload_data[0] = reg_offset; 480 memcpy(&payload_data[1], (data + 7), payload_size); 481 482 msg.addr = slave_addr; 483 msg.flags = 0; 484 msg.len = payload_size + 1; 485 msg.buf = payload_data; 486 487 ret = i2c_transfer(adapter, &msg, 1); 488 if (ret < 0) 489 DRM_DEV_ERROR(dev, 490 "Failed to xfer payload of size (%u) to reg (%u)\n", 491 payload_size, reg_offset); 492 493 kfree(payload_data); 494 err_alloc: 495 i2c_put_adapter(adapter); 496 err_bus: 497 return data + payload_size + 7; 498 } 499 500 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 501 { 502 DRM_DEBUG_KMS("Skipping SPI element execution\n"); 503 504 return data + *(data + 5) + 6; 505 } 506 507 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 508 { 509 #ifdef CONFIG_PMIC_OPREGION 510 u32 value, mask, reg_address; 511 u16 i2c_address; 512 int ret; 513 514 /* byte 0 aka PMIC Flag is reserved */ 515 i2c_address = get_unaligned_le16(data + 1); 516 reg_address = get_unaligned_le32(data + 3); 517 value = get_unaligned_le32(data + 7); 518 mask = get_unaligned_le32(data + 11); 519 520 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 521 reg_address, 522 value, mask); 523 if (ret) 524 DRM_ERROR("%s failed, error: %d\n", __func__, ret); 525 #else 526 DRM_ERROR("Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 527 #endif 528 529 return data + 15; 530 } 531 532 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 533 const u8 *data); 534 static const fn_mipi_elem_exec exec_elem[] = { 535 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 536 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 537 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 538 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 539 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 540 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 541 }; 542 543 /* 544 * MIPI Sequence from VBT #53 parsing logic 545 * We have already separated each seqence during bios parsing 546 * Following is generic execution function for any sequence 547 */ 548 549 static const char * const seq_name[] = { 550 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 551 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 552 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 553 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 554 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 555 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 556 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 557 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 558 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 559 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 560 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 561 }; 562 563 static const char *sequence_name(enum mipi_seq seq_id) 564 { 565 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 566 return seq_name[seq_id]; 567 else 568 return "(unknown)"; 569 } 570 571 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 572 enum mipi_seq seq_id) 573 { 574 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 575 const u8 *data; 576 fn_mipi_elem_exec mipi_elem_exec; 577 578 if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) 579 return; 580 581 data = dev_priv->vbt.dsi.sequence[seq_id]; 582 if (!data) 583 return; 584 585 WARN_ON(*data != seq_id); 586 587 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n", 588 seq_id, sequence_name(seq_id)); 589 590 /* Skip Sequence Byte. */ 591 data++; 592 593 /* Skip Size of Sequence. */ 594 if (dev_priv->vbt.dsi.seq_version >= 3) 595 data += 4; 596 597 while (1) { 598 u8 operation_byte = *data++; 599 u8 operation_size = 0; 600 601 if (operation_byte == MIPI_SEQ_ELEM_END) 602 break; 603 604 if (operation_byte < ARRAY_SIZE(exec_elem)) 605 mipi_elem_exec = exec_elem[operation_byte]; 606 else 607 mipi_elem_exec = NULL; 608 609 /* Size of Operation. */ 610 if (dev_priv->vbt.dsi.seq_version >= 3) 611 operation_size = *data++; 612 613 if (mipi_elem_exec) { 614 const u8 *next = data + operation_size; 615 616 data = mipi_elem_exec(intel_dsi, data); 617 618 /* Consistency check if we have size. */ 619 if (operation_size && data != next) { 620 DRM_ERROR("Inconsistent operation size\n"); 621 return; 622 } 623 } else if (operation_size) { 624 /* We have size, skip. */ 625 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n", 626 operation_byte); 627 data += operation_size; 628 } else { 629 /* No size, can't skip without parsing. */ 630 DRM_ERROR("Unsupported MIPI operation byte %u\n", 631 operation_byte); 632 return; 633 } 634 } 635 } 636 637 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 638 enum mipi_seq seq_id) 639 { 640 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 641 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 642 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 643 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 644 645 intel_dsi_vbt_exec(intel_dsi, seq_id); 646 647 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 648 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 649 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 650 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 651 } 652 653 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 654 { 655 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 656 657 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 658 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) 659 return; 660 661 msleep(msec); 662 } 663 664 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 665 { 666 DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk); 667 DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap); 668 DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count); 669 DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 670 DRM_DEBUG_KMS("Video mode format %s\n", 671 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ? 672 "non-burst with sync pulse" : 673 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ? 674 "non-burst with sync events" : 675 intel_dsi->video_mode_format == VIDEO_MODE_BURST ? 676 "burst" : "<unknown>"); 677 DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio); 678 DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val); 679 DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt)); 680 DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop)); 681 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); 682 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 683 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 684 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 685 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 686 else 687 DRM_DEBUG_KMS("Dual link: NONE\n"); 688 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); 689 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); 690 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); 691 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); 692 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count); 693 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); 694 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 695 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 696 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); 697 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); 698 DRM_DEBUG_KMS("BTA %s\n", 699 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 700 } 701 702 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 703 { 704 struct drm_device *dev = intel_dsi->base.base.dev; 705 struct drm_i915_private *dev_priv = to_i915(dev); 706 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 707 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; 708 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; 709 u16 burst_mode_ratio; 710 enum port port; 711 712 DRM_DEBUG_KMS("\n"); 713 714 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 715 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 716 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 717 intel_dsi->pixel_format = 718 pixel_format_from_register_bits( 719 mipi_config->videomode_color_format << 7); 720 721 intel_dsi->dual_link = mipi_config->dual_link; 722 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 723 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 724 intel_dsi->video_mode_format = mipi_config->video_transfer_mode; 725 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 726 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 727 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 728 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 729 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 730 intel_dsi->init_count = mipi_config->master_init_timer; 731 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 732 intel_dsi->video_frmt_cfg_bits = 733 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 734 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 735 736 /* Starting point, adjusted depending on dual link and burst mode */ 737 intel_dsi->pclk = mode->clock; 738 739 /* In dual link mode each port needs half of pixel clock */ 740 if (intel_dsi->dual_link) { 741 intel_dsi->pclk /= 2; 742 743 /* we can enable pixel_overlap if needed by panel. In this 744 * case we need to increase the pixelclock for extra pixels 745 */ 746 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 747 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 748 } 749 } 750 751 /* Burst Mode Ratio 752 * Target ddr frequency from VBT / non burst ddr freq 753 * multiply by 100 to preserve remainder 754 */ 755 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 756 if (mipi_config->target_burst_mode_freq) { 757 u32 bitrate = intel_dsi_bitrate(intel_dsi); 758 759 /* 760 * Sometimes the VBT contains a slightly lower clock, 761 * then the bitrate we have calculated, in this case 762 * just replace it with the calculated bitrate. 763 */ 764 if (mipi_config->target_burst_mode_freq < bitrate && 765 intel_fuzzy_clock_check( 766 mipi_config->target_burst_mode_freq, 767 bitrate)) 768 mipi_config->target_burst_mode_freq = bitrate; 769 770 if (mipi_config->target_burst_mode_freq < bitrate) { 771 DRM_ERROR("Burst mode freq is less than computed\n"); 772 return false; 773 } 774 775 burst_mode_ratio = DIV_ROUND_UP( 776 mipi_config->target_burst_mode_freq * 100, 777 bitrate); 778 779 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 780 } else { 781 DRM_ERROR("Burst mode target is not set\n"); 782 return false; 783 } 784 } else 785 burst_mode_ratio = 100; 786 787 intel_dsi->burst_mode_ratio = burst_mode_ratio; 788 789 /* delays in VBT are in unit of 100us, so need to convert 790 * here in ms 791 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 792 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 793 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 794 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 795 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 796 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 797 798 intel_dsi->i2c_bus_num = -1; 799 800 /* a regular driver would get the device in probe */ 801 for_each_dsi_port(port, intel_dsi->ports) { 802 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 803 } 804 805 return true; 806 } 807 808 /* 809 * On some BYT/CHT devs some sequences are incomplete and we need to manually 810 * control some GPIOs. We need to add a GPIO lookup table before we get these. 811 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 812 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 813 */ 814 static struct gpiod_lookup_table pmic_panel_gpio_table = { 815 /* Intel GFX is consumer */ 816 .dev_id = "0000:00:02.0", 817 .table = { 818 /* Panel EN/DISABLE */ 819 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 820 { } 821 }, 822 }; 823 824 static struct gpiod_lookup_table soc_panel_gpio_table = { 825 .dev_id = "0000:00:02.0", 826 .table = { 827 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 828 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 829 { } 830 }, 831 }; 832 833 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 834 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 835 "pwm0_grp", "pwm"), 836 }; 837 838 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 839 { 840 struct drm_device *dev = intel_dsi->base.base.dev; 841 struct drm_i915_private *dev_priv = to_i915(dev); 842 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 843 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 844 bool want_backlight_gpio = false; 845 bool want_panel_gpio = false; 846 struct pinctrl *pinctrl; 847 int ret; 848 849 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 850 mipi_config->pwm_blc == PPS_BLC_PMIC) { 851 gpiod_add_lookup_table(&pmic_panel_gpio_table); 852 want_panel_gpio = true; 853 } 854 855 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 856 gpiod_add_lookup_table(&soc_panel_gpio_table); 857 want_panel_gpio = true; 858 want_backlight_gpio = true; 859 860 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 861 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 862 ARRAY_SIZE(soc_pwm_pinctrl_map)); 863 if (ret) 864 DRM_ERROR("Failed to register pwm0 pinmux mapping\n"); 865 866 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 867 if (IS_ERR(pinctrl)) 868 DRM_ERROR("Failed to set pinmux to PWM\n"); 869 } 870 871 if (want_panel_gpio) { 872 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 873 if (IS_ERR(intel_dsi->gpio_panel)) { 874 DRM_ERROR("Failed to own gpio for panel control\n"); 875 intel_dsi->gpio_panel = NULL; 876 } 877 } 878 879 if (want_backlight_gpio) { 880 intel_dsi->gpio_backlight = 881 gpiod_get(dev->dev, "backlight", flags); 882 if (IS_ERR(intel_dsi->gpio_backlight)) { 883 DRM_ERROR("Failed to own gpio for backlight control\n"); 884 intel_dsi->gpio_backlight = NULL; 885 } 886 } 887 } 888 889 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 890 { 891 struct drm_device *dev = intel_dsi->base.base.dev; 892 struct drm_i915_private *dev_priv = to_i915(dev); 893 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 894 895 if (intel_dsi->gpio_panel) { 896 gpiod_put(intel_dsi->gpio_panel); 897 intel_dsi->gpio_panel = NULL; 898 } 899 900 if (intel_dsi->gpio_backlight) { 901 gpiod_put(intel_dsi->gpio_backlight); 902 intel_dsi->gpio_backlight = NULL; 903 } 904 905 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 906 mipi_config->pwm_blc == PPS_BLC_PMIC) 907 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 908 909 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 910 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 911 gpiod_remove_lookup_table(&soc_panel_gpio_table); 912 } 913 } 914
Indexes created Sat Sep 20 22:09:52 GMT 2025