| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen_cs.c | 1178 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1250 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1262 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1274 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1286 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1310 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1330 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1534 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1551 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1592 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff)
[all...] |
| radeon_r600_cs.c | 1026 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1088 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1090 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;
1109 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1218 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1249 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1285 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1288 track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
1299 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1301 track->db_bo_mc = reloc->gpu_offset;
[all...] |
| radeon_r200.c | 196 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
209 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
233 ib[idx] = tmp + ((u32)reloc->gpu_offset);
235 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
279 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
373 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
|
| radeon_r300.c | 708 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
721 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
750 ((idx_value & ~31) + (u32)reloc->gpu_offset);
759 tmp = idx_value + ((u32)reloc->gpu_offset);
1120 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1165 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1230 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
|
| radeon_r100.c | 1299 tmp += (((u32)reloc->gpu_offset) >> 10);
1350 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1362 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1376 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1617 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1630 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1651 ib[idx] = tmp + ((u32)reloc->gpu_offset);
1653 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1671 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1689 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
[all...] |
| radeon_cs.c | 892 (*cs_reloc)->gpu_offset =
894 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
|
| radeon_object.c | 608 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
613 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
|
| radeon_ttm.c | 102 man->gpu_offset = rdev->mc.gtt_start;
124 man->gpu_offset = rdev->mc.vram_start;
|
| radeon_uvd.c | 599 start = reloc->gpu_offset;
|
| radeon_vce.c | 546 start = reloc->gpu_offset;
|
| radeon.h | 480 uint64_t gpu_offset; member in struct:radeon_bo_list
|
| /src/sys/external/bsd/drm2/dist/drm/qxl/ |
| qxl_ttm.c | 81 slot->gpu_offset = (uint64_t)type << gpu_offset_shift;
83 man->gpu_offset = slot->gpu_offset;
|
| qxl_drv.h | 139 uint64_t gpu_offset; member in struct:qxl_memslot
316 WARN_ON_ONCE((bo->tbo.offset & slot->gpu_offset) != slot->gpu_offset);
319 return slot->high_bits | (bo->tbo.offset - slot->gpu_offset + offset);
|
| qxl_kms.c | 94 DRM_INFO("slot %d (%s): base 0x%08lx, size 0x%08lx, gpu_offset 0x%lx\n",
98 (unsigned long)slot->gpu_offset);
|
| /src/sys/external/bsd/drm2/dist/include/drm/ttm/ |
| ttm_bo_driver.h | 147 * @gpu_offset: If used, the GPU offset of the first managed page of
182 uint64_t gpu_offset; /* GPU address space is independent of CPU word size */ member in struct:ttm_mem_type_manager
|
| /src/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
| vmwgfx_ttm_buffer.c | 763 man->gpu_offset = 0;
776 man->gpu_offset = 0;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_ttm.c | 112 man->gpu_offset = adev->gmc.gart_start;
120 man->gpu_offset = adev->gmc.vram_start;
131 man->gpu_offset = 0;
284 addr += bo->bdev->man[mem->mem_type].gpu_offset;
1209 bo->bdev->man[bo->mem.mem_type].gpu_offset;
|
| amdgpu_object.c | 927 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
|
| /src/sys/external/bsd/drm2/dist/drm/ttm/ |
| ttm_bo.c | 112 drm_printf(p, " gpu_offset: 0x%08"PRIX64"\n", man->gpu_offset);
412 bdev->man[bo->mem.mem_type].gpu_offset;
|
