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    Searched refs:grph (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hubbub.c 287 output->grph.rgb.max_uncompressed_blk_size = 256;
288 output->grph.rgb.max_compressed_blk_size = 256;
289 output->grph.rgb.independent_64b_blks = false;
292 output->grph.rgb.max_uncompressed_blk_size = 128;
293 output->grph.rgb.max_compressed_blk_size = 128;
294 output->grph.rgb.independent_64b_blks = false;
297 output->grph.rgb.max_uncompressed_blk_size = 256;
298 output->grph.rgb.max_compressed_blk_size = 64;
299 output->grph.rgb.independent_64b_blks = true;
amdgpu_dcn20_hubp.c 718 * base on address->grph.dcc_const_color
723 if (address->grph.addr.quad_part == 0)
730 if (address->grph.meta_addr.quad_part != 0) {
733 address->grph.meta_addr.high_part);
737 address->grph.meta_addr.low_part);
742 address->grph.addr.high_part);
746 address->grph.addr.low_part);
900 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
903 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
908 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_debug.c 79 "plane_state->address.grph.addr.quad_part = 0x%"PRIX64";\n"
80 "plane_state->address.grph.meta_addr.quad_part = 0x%"PRIX64";\n"
88 plane_state->address.grph.addr.quad_part,
89 plane_state->address.grph.meta_addr.quad_part,
196 "flip_addr->address.grph.addr.quad_part = 0x%"PRIX64";\n"
197 "flip_addr->address.grph.meta_addr.quad_part = 0x%"PRIX64";\n"
200 update->flip_addr->address.grph.addr.quad_part,
201 update->flip_addr->address.grph.meta_addr.quad_part,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hubbub.c 924 output->grph.rgb.max_uncompressed_blk_size = 256;
925 output->grph.rgb.max_compressed_blk_size = 256;
926 output->grph.rgb.independent_64b_blks = false;
929 output->grph.rgb.max_uncompressed_blk_size = 128;
930 output->grph.rgb.max_compressed_blk_size = 128;
931 output->grph.rgb.independent_64b_blks = false;
934 output->grph.rgb.max_uncompressed_blk_size = 256;
935 output->grph.rgb.max_compressed_blk_size = 64;
936 output->grph.rgb.independent_64b_blks = true;
amdgpu_dcn10_hubp.c 376 * base on address->grph.dcc_const_color
381 if (address->grph.addr.quad_part == 0)
388 if (address->grph.meta_addr.quad_part != 0) {
391 address->grph.meta_addr.high_part);
395 address->grph.meta_addr.low_part);
400 address->grph.addr.high_part);
404 address->grph.addr.low_part);
734 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
737 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
742 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hubp.c 810 if (address->grph.addr.quad_part == 0) {
815 if (address->grph.meta_addr.quad_part != 0) {
817 address->grph.meta_addr.low_part;
819 address->grph.meta_addr.high_part;
823 address->grph.addr.low_part;
825 address->grph.addr.high_part;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_mem_input.c 494 DC_ERR("unsupported grph pixel format");
710 if (address->grph.addr.quad_part == 0)
712 program_pri_addr(dce_mi, address->grph.addr);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_hw_types.h 77 } grph; member in union:dc_plane_address::__anon788fbb99030a
dc.h 150 } grph; member in union:dc_surface_dcc_cap::__anon04b89587040a
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_mem_input_v.c 143 addr->grph.addr);
amdgpu_dce110_hw_sequencer.c 1853 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2538 pipe_ctx->plane_state->address.grph.addr.high_part,
2539 pipe_ctx->plane_state->address.grph.addr.low_part,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c 3186 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
3195 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
3196 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
3229 address->grph.addr.low_part = lower_32_bits(afb->address);
3230 address->grph.addr.high_part = upper_32_bits(afb->address);
6489 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
6490 bundle->flip_addrs[planes_count].address.grph.addr.low_part);

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