| /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/ |
| intel_guc_submission.h | 16 void intel_guc_submission_init_early(struct intel_guc *guc);
17 int intel_guc_submission_init(struct intel_guc *guc);
18 void intel_guc_submission_enable(struct intel_guc *guc);
19 void intel_guc_submission_disable(struct intel_guc *guc);
20 void intel_guc_submission_fini(struct intel_guc *guc);
21 int intel_guc_preempt_work_create(struct intel_guc *guc);
22 void intel_guc_preempt_work_destroy(struct intel_guc *guc);
|
| intel_guc_ads.h | 13 int intel_guc_ads_create(struct intel_guc *guc);
14 void intel_guc_ads_destroy(struct intel_guc *guc);
15 void intel_guc_ads_reset(struct intel_guc *guc);
|
| intel_guc_fw.h | 13 void intel_guc_fw_init_early(struct intel_guc *guc);
14 int intel_guc_fw_upload(struct intel_guc *guc);
|
| intel_guc.h | 24 * Top level structure of GuC. It handles firmware loading and manages client
39 void (*reset)(struct intel_guc *guc);
40 void (*enable)(struct intel_guc *guc);
41 void (*disable)(struct intel_guc *guc);
62 /* GuC's FW specific registers used in MMIO send */
69 /* register used to send interrupts to the GuC FW */
80 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
82 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0);
86 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
89 return intel_guc_ct_send(&guc->ct, action, len
[all...] |
| intel_guc.c | 22 * DOC: GuC
24 * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is
29 * - Low latency graphics context scheduling (a.k.a. GuC submission).
33 * operations to enable within GuC. Note that not all the operations are
36 * Enabling the GuC is not mandatory and therefore the firmware is only loaded
37 * if at least one of the operations is selected. However, not loading the GuC
38 * might result in the loss of some features that do require the GuC (currently
42 void intel_guc_notify(struct intel_guc *guc)
44 struct intel_gt *gt = guc_to_gt(guc);
[all...] |
| intel_uc.c | 23 /* Reset GuC providing us with fresh state for both GuC and HuC.
37 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
43 "GuC status: 0x%x, MIA core expected to be in reset\n",
54 "enable_guc=%d (guc:%s submission:%s huc:%s)\n",
73 i915_modparams.enable_guc, "GuC is not supported!");
85 i915_modparams.enable_guc, "GuC submission is N/A");
96 intel_guc_init_early(&uc->guc);
120 intel_guc_init_send_regs(&uc->guc);
125 struct intel_guc *guc = &uc->guc local
283 struct intel_guc *guc = &uc->guc; local
312 struct intel_guc *guc = &uc->guc; local
405 struct intel_guc *guc = &uc->guc; local
511 struct intel_guc *guc = &uc->guc; local
533 struct intel_guc *guc = &uc->guc; local
544 struct intel_guc *guc = &uc->guc; local
559 struct intel_guc *guc = &uc->guc; local
571 struct intel_guc *guc = &uc->guc; local
[all...] |
| intel_guc_submission.c | 27 * DOC: GuC-based command submission
29 * IMPORTANT NOTE: GuC submission is currently not supported in i915. The GuC
35 * GuC stage descriptor:
37 * descriptors, and shares them with the GuC. Currently, we only use one
38 * descriptor. This stage descriptor lets the GuC know about the workqueue and
39 * process descriptor. Theoretically, it also lets the GuC know about our HW
41 * where the GuC uses the LRCA sent via the work item instead. This is called
47 * triggers an interrupt on the GuC via another register write (0xC4C8).
55 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, whic
250 struct intel_guc *guc = &engine->gt->uc.guc; local
[all...] |
| intel_guc_ads.c | 18 * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
20 * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
62 /* The ads obj includes the struct itself and buffers passed to GuC */
73 static void __guc_ads_init(struct intel_guc *guc)
75 struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
76 struct __guc_ads_blob *blob = guc->ads_blob;
81 /* GuC scheduling policies */
85 * GuC expects a per-engine-class context image and size
89 * we have told GuC where to find it. The context size will be used
97 * GuC to re-init guilty contexts after internal reset
[all...] |
| intel_guc_fw.c | 22 * intel_guc_fw_init_early() - initializes GuC firmware struct
23 * @guc: intel_guc struct
25 * On platforms with GuC selects firmware for uploading
27 void intel_guc_fw_init_early(struct intel_guc *guc)
29 struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
31 intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, HAS_GT_UC(i915),
53 /* DOP Clock Gating Enable for GuC clocks */
78 * Read the GuC status register (GUC_STATUS) and store it in the
81 * of the GuC boot process.
83 * This is used for polling the GuC status in a wait_for(
[all...] |
| intel_uc.h | 29 struct intel_guc guc; member in struct:intel_uc
32 /* Snapshot of GuC log from last failed load */
47 return intel_guc_is_supported(&uc->guc);
52 return intel_guc_is_enabled(&uc->guc);
57 return intel_guc_is_submission_supported(&uc->guc);
62 return intel_guc_is_submission_supported(&uc->guc);
|
| intel_guc_log.c | 21 * DOC: GuC firmware log
29 static int guc_action_flush_log_complete(struct intel_guc *guc)
35 return intel_guc_send(guc, action, ARRAY_SIZE(action));
38 static int guc_action_flush_log(struct intel_guc *guc)
45 return intel_guc_send(guc, action, ARRAY_SIZE(action));
48 static int guc_action_control_log(struct intel_guc *guc, bool enable,
60 return intel_guc_send(guc, action, ARRAY_SIZE(action));
201 "GuC log buffer overflow\n");
237 /* Get the pointer to shared GuC log buffer */
260 * Make a copy of the state structure, inside GuC log buffe
374 struct intel_guc *guc = log_to_guc(log); local
421 struct intel_guc *guc = log_to_guc(log); local
460 struct intel_guc *guc = log_to_guc(log); local
518 struct intel_guc *guc = log_to_guc(log); local
626 struct intel_guc *guc = log_to_guc(log); local
652 struct intel_guc *guc = log_to_guc(log); local
[all...] |
| intel_huc.c | 25 * triggering its security authentication, which is performed by the GuC. For
26 * The GuC to correctly perform the authentication, the HuC binary must be
27 * loaded before the GuC one. Loading the HuC is optional; however, not using
38 * Similarly to the GuC, the HuC can't do any memory allocations on its own,
65 struct intel_guc *guc = >->uc.guc; local
77 * through GTT. Unfortunately, this means GuC cannot perform
78 * the HuC auth. as the rsa offset now falls within the GuC
81 * signature. The GuC can use this extra pinning to perform
82 * the authentication since its GGTT offset will be GuC
161 struct intel_guc *guc = >->uc.guc; local
[all...] |
| intel_guc_ct.c | 87 static int guc_action_register_ct_buffer(struct intel_guc *guc,
100 err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
107 static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
118 err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
135 struct intel_guc *guc = ct_to_guc(ct); local
164 err = intel_guc_allocate_and_map_vma(guc, PAGE_SIZE, &ct->vma, &blob);
171 intel_guc_ggtt_offset(guc, ct->vma));
205 struct intel_guc *guc = ct_to_guc(ct); local
214 base = intel_guc_ggtt_offset(guc, ct->vma);
229 err = guc_action_register_ct_buffer(guc,
259 struct intel_guc *guc = ct_to_guc(ct); local
548 struct intel_guc *guc = ct_to_guc(ct); local
719 struct intel_guc *guc = ct_to_guc(ct); local
[all...] |
| intel_uc_fw.c | 23 return container_of(uc_fw, struct intel_gt, uc.guc.fw);
43 * List of required GuC and HuC binaries per-platform.
152 /* We don't want to enable GuC/HuC on pre-Gen11 by default */
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| intel_wopcm.h | 17 * @guc: GuC WOPCM Region info.
18 * @guc.base: GuC WOPCM base which is offset from WOPCM base.
19 * @guc.size: Size of the GuC WOPCM region.
26 } guc; member in struct:intel_wopcm
36 * 0 if GuC is not present or not in use.
37 * Otherwise, the GuC WOPCM base.
41 return wopcm->guc.base
[all...] |
| intel_wopcm.c | 19 * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
20 * offset registers whose values are calculated and determined by HuC/GuC
27 * | +===> +====================+ <== GuC WOPCM Top
31 * | GuC | |
34 * WOPCM | | GuC FW RSVD |
36 * | | | GuC Stack RSVD |
38 * | v | GuC WOPCM RSVD |
39 * | +===> +====================+ <== GuC WOPCM base
45 * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top
[all...] |
| i915_debugfs.c | 517 seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
642 seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
1720 intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p);
1763 struct intel_guc_log *log = &dev_priv->gt.uc.guc.log;
1767 seq_puts(m, "GuC log relay not created\n");
1771 seq_puts(m, "GuC logging stats:\n");
1801 const struct intel_guc *guc = &dev_priv->gt.uc.guc; local
1802 struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
1814 seq_printf(m, "GuC stage descriptor %u:\n", index)
1918 struct intel_guc *guc = &i915->gt.uc.guc; local
1958 struct intel_guc *guc = &i915->gt.uc.guc; local
[all...] |
| i915_gpu_error.c | 1516 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1523 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
1527 uc->guc.log.vma, "GuC log buffer",
|
| i915_drv.h | 1760 /* Having GuC is not the same as using GuC */
2096 static inline bool intel_guc_submission_is_enabled(struct intel_guc *guc)
2098 return intel_guc_is_submission_supported(guc) &&
2099 intel_guc_is_running(guc);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_gt.h | 28 static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
30 return container_of(guc, struct intel_gt, uc.guc);
|
| intel_gt_irq.c | 21 static void guc_irq_handler(struct intel_guc *guc, u16 iir)
24 intel_guc_to_host_event_handler(guc);
82 return guc_irq_handler(>->uc.guc, iir);
242 /* Same thing for GuC interrupts */
342 guc_irq_handler(>->uc.guc, gt_iir[2] >> 16);
384 * is enabled/disabled. Same wil be the case for GuC interrupts.
|
| intel_reset.c | 1143 ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
1147 uses_guc ? "GuC " : "",
|
