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    Searched refs:h_addressable (Results 1 - 25 of 25) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/include/
bios_parser_types.h 166 uint32_t h_addressable; member in struct:bp_hw_crtc_timing_parameters
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
amdgpu_command_table2.c 498 params.h_size = cpu_to_le16((uint16_t)bp_params->h_addressable);
502 bp_params->h_addressable));
515 bp_params->h_addressable));
amdgpu_command_table.c 1758 params.usH_Disp = cpu_to_le16((uint16_t)(bp_params->h_addressable));
1831 params.usH_Size = cpu_to_le16((uint16_t)bp_params->h_addressable);
1834 cpu_to_le16((uint16_t)(bp_params->h_total - bp_params->h_addressable));
1844 cpu_to_le16((uint16_t)(bp_params->h_sync_start - bp_params->h_addressable));
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator.c 301 uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset;
316 bp_params.h_addressable =
317 patched_crtc_timing.h_addressable;
616 uint32_t h_sync_start = timing->h_addressable + hsync_offset;
675 tmp = tmp + timing->h_addressable +
1135 h_sync_start = timing->h_addressable + hsync_offset;
1154 h_blank = (timing->h_total - timing->h_addressable -
1165 timing->h_addressable -
amdgpu_dce110_timing_generator_v.c 257 uint32_t h_sync_start = timing->h_addressable + hsync_offset;
294 tmp = tmp + timing->h_addressable +
amdgpu_dce110_hw_sequencer.c 680 timing->h_addressable
1132 stream->timing.h_addressable
1858 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
amdgpu_dce110_resource.c 964 context->streams[0]->timing.h_addressable,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_opp.c 319 uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right;
amdgpu_dcn10_optc.c 192 patched_crtc_timing.h_addressable -
528 h_blank = (timing->h_total - timing->h_addressable -
1259 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
amdgpu_dcn10_stream_encoder.c 442 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
474 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_hwss.c 433 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
537 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
amdgpu_dc.c 364 param.windowa_x_end = pipe->stream->timing.h_addressable;
368 param.windowb_x_end = pipe->stream->timing.h_addressable;
1103 if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1276 context->streams[i]->timing.h_addressable,
amdgpu_dc_resource.c 377 if (stream1->timing.h_addressable
378 != stream2->timing.h_addressable)
1025 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
amdgpu_dc_link_dp.c 2225 timing->h_addressable == (uint32_t) 640 &&
3635 int width = pipe_ctx->stream->timing.h_addressable +
amdgpu_dc_link.c 2079 bool is_vga_mode = (stream->timing.h_addressable == 640)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_hw_types.h 717 uint32_t h_addressable; member in struct:dc_crtc_timing
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_optc.c 244 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
amdgpu_dcn20_resource.c 1944 - timing->h_addressable
1954 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
2073 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2304 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
amdgpu_dcn20_hwseq.c 949 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
2244 timing->h_addressable
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_stream_encoder.c 484 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
520 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c 445 uint32_t h_sync_start = timing->h_addressable + hsync_offset;
473 tmp2 = tmp1 + timing->h_addressable +
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
amdgpu_dc_dsc.c 585 pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 425 - pipe->stream->timing.h_addressable
894 v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
amdgpu_dce_calcs.c 2967 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c 3572 dst.width = stream->timing.h_addressable;
3592 dst.x = (stream->timing.h_addressable - dst.width) / 2;
3822 timing_out->h_addressable = mode_in->crtc_hdisplay;

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