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    Searched refs:h_border_left (Results 1 - 18 of 18) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator_v.c 286 (h_sync_start + timing->h_border_left);
295 timing->h_border_left + timing->h_border_right;
amdgpu_dce110_timing_generator.c 328 patched_crtc_timing.h_border_left;
667 (h_sync_start + timing->h_border_left);
676 timing->h_border_left + timing->h_border_right;
1156 timing->h_border_left);
amdgpu_dce110_hw_sequencer.c 681 + timing->h_border_left
1133 + stream->timing.h_border_left
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_hwss.c 433 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
537 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
amdgpu_dc_resource.c 950 * stream->timing.h_border_left that is non zero. If we are doing
951 * pipe-splitting, this h_border_left value gets added to recout.x and when it
956 * To fix this, instead of using stream->timing.h_border_left, we can use
957 * stream->dst.x to represent the border instead. So we will set h_border_left
960 * and then restore the h_border_left and stream->dst.x to their original
963 * shift_border_left_to_dst() will shift the amount of h_border_left to
964 * stream->dst.x and set h_border_left to 0. restore_border_left_from_dst()
965 * will restore h_border_left and stream->dst.x back to their original values
967 * original h_border_left value in its calculation.
971 int store_h_border_left = pipe_ctx->stream->timing.h_border_left;
    [all...]
amdgpu_dc.c 1100 if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
amdgpu_dc_link_dp.c 3636 pipe_ctx->stream->timing.h_border_left +
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_hw_types.h 716 uint32_t h_border_left; member in struct:dc_crtc_timing
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_optc.c 244 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
amdgpu_dcn20_hwseq.c 949 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
2245 + timing->h_border_left
amdgpu_dcn20_resource.c 1945 - timing->h_border_left
2304 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_stream_encoder.c 483 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
519 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c 472 (h_sync_start + timing->h_border_left);
474 timing->h_border_left + timing->h_border_right;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_optc.c 193 patched_crtc_timing.h_border_left;
530 timing->h_border_left);
amdgpu_dcn10_stream_encoder.c 441 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
473 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
amdgpu_dc_dsc.c 585 pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 426 - pipe->stream->timing.h_border_left
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c 3779 timing_out->h_border_left = 0;

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