/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
amdgpu_dcn20_dpp.c | 409 if (in_taps->h_taps == 0) { 411 scl_data->taps.h_taps = 8; 413 scl_data->taps.h_taps = 4; 415 scl_data->taps.h_taps = in_taps->h_taps; 443 scl_data->taps.h_taps = 1;
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amdgpu_dcn20_dwb_scl.c | 730 uint32_t h_taps_luma = num_taps.h_taps;
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amdgpu_dcn20_resource.c | 2157 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
amdgpu_dcn10_dpp.c | 174 if (in_taps->h_taps == 0) 175 scl_data->taps.h_taps = 4; 177 scl_data->taps.h_taps = in_taps->h_taps; 196 scl_data->taps.h_taps = 1;
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amdgpu_dcn10_dpp_dscl.c | 318 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 320 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); 340 scl_data->taps.h_taps, scl_data->ratios.horz); 361 dpp, scl_data->taps.h_taps, 574 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, 734 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
amdgpu_dce_transform.c | 127 if (data->taps.h_taps + data->taps.v_taps <= 2) { 137 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, 272 dc_fixpt_from_int(data->taps.h_taps + 1)), 358 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); 382 data->taps.h_taps, 387 data->taps.h_taps, 927 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); 929 scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true);
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
amdgpu_dce110_transform_v.c | 172 set_reg_field_value(value, data->taps.h_taps - 1, 183 if (data->taps.h_taps + data->taps.v_taps > 2) { 568 coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz); 591 data->taps.h_taps,
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
amdgpu_dc_debug.c | 81 "plane_state->scaling_quality.h_taps = %d;\n" 90 plane_state->scaling_quality.h_taps, 278 "scaling_info->scaling_quality.h_taps = %d;\n" 294 update->scaling_info->scaling_quality.h_taps,
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amdgpu_dc_resource.c | 890 dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19); 909 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps, 927 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps,
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
dc_hw_types.h | 581 uint32_t h_taps; member in struct:scaling_taps
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
dce_calcs.h | 398 struct bw_fixed h_taps[maximum_number_of_surfaces]; member in struct:bw_calcs_data
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
amdgpu_dce_calcs.c | 372 data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); 373 data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); 426 data->h_taps[i] = bw_int_to_fixed(1); 516 if (bw_mtn(data->hsr[i], data->h_taps[i])) { 520 if (dceip->pre_downscaler_enabled == 1 && bw_mtn(data->hsr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)))) { 1252 data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1)))); 1703 data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1)))); 2807 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); 2862 data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps) [all...] |
calcs_logger.h | 432 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_taps[%d]:%d", i, bw_fixed_to_int(data->h_taps[i]));
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amdgpu_dcn_calcs.c | 389 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; 986 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
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