1 /* $NetBSD: amdgpu_dcn_calcs.c,v 1.4 2023/07/20 21:48:49 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * Copyright 2019 Raptor Engineering, LLC 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: AMD 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn_calcs.c,v 1.4 2023/07/20 21:48:49 riastradh Exp $"); 31 32 #include "dm_services.h" 33 #include "dc.h" 34 #include "dcn_calcs.h" 35 #include "dcn_calc_auto.h" 36 #include "dal_asic_id.h" 37 #include "resource.h" 38 #include "dcn10/dcn10_resource.h" 39 #include "dcn10/dcn10_hubbub.h" 40 #include "dml/dml1_display_rq_dlg_calc.h" 41 42 #include "dcn_calc_math.h" 43 44 #define DC_LOGGER \ 45 dc->ctx->logger 46 47 #define WM_SET_COUNT 4 48 #define WM_A 0 49 #define WM_B 1 50 #define WM_C 2 51 #define WM_D 3 52 53 /* 54 * NOTE: 55 * This file is gcc-parseable HW gospel, coming straight from HW engineers. 56 * 57 * It doesn't adhere to Linux kernel style and sometimes will do things in odd 58 * ways. Unless there is something clearly wrong with it the code should 59 * remain as-is as it provides us with a guarantee from HW that it is correct. 60 */ 61 62 /* Defaults from spreadsheet rev#247. 63 * RV2 delta: dram_clock_change_latency, max_num_dpp 64 */ 65 const struct dcn_soc_bounding_box dcn10_soc_defaults = { 66 /* latencies */ 67 .sr_exit_time = 17, /*us*/ 68 .sr_enter_plus_exit_time = 19, /*us*/ 69 .urgent_latency = 4, /*us*/ 70 .dram_clock_change_latency = 17, /*us*/ 71 .write_back_latency = 12, /*us*/ 72 .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/ 73 74 /* below default clocks derived from STA target base on 75 * slow-slow corner + 10% margin with voltages aligned to FCLK. 76 * 77 * Use these value if fused value doesn't make sense as earlier 78 * part don't have correct value fused */ 79 /* default DCF CLK DPM on RV*/ 80 .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5 */ 81 .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75 */ 82 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */ 83 .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */ 84 85 /* default DISP CLK voltage state on RV */ 86 .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25 */ 87 .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5 */ 88 .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75 */ 89 .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75 */ 90 91 /* default DPP CLK voltage state on RV */ 92 .max_dppclk_vmax0p9 = 720, /* MHz, = 3600/5 */ 93 .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25 */ 94 .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */ 95 .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */ 96 97 /* default PHY CLK voltage state on RV */ 98 .phyclkv_max0p9 = 900, /*MHz*/ 99 .phyclkv_nom0p8 = 847, /*MHz*/ 100 .phyclkv_mid0p72 = 800, /*MHz*/ 101 .phyclkv_min0p65 = 600, /*MHz*/ 102 103 /* BW depend on FCLK, MCLK, # of channels */ 104 /* dual channel BW */ 105 .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/ 106 .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/ 107 .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/ 108 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/ 109 /* single channel BW 110 .fabric_and_dram_bandwidth_vmax0p9 = 19.2f, 111 .fabric_and_dram_bandwidth_vnom0p8 = 17.066f, 112 .fabric_and_dram_bandwidth_vmid0p72 = 14.933f, 113 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, 114 */ 115 116 .number_of_channels = 2, 117 118 .socclk = 208, /*MHz*/ 119 .downspreading = 0.5f, /*%*/ 120 .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/ 121 .urgent_out_of_order_return_per_channel = 256, /*bytes*/ 122 .vmm_page_size = 4096, /*bytes*/ 123 .return_bus_width = 64, /*bytes*/ 124 .max_request_size = 256, /*bytes*/ 125 126 /* Depends on user class (client vs embedded, workstation, etc) */ 127 .percent_disp_bw_limit = 0.3f /*%*/ 128 }; 129 130 const struct dcn_ip_params dcn10_ip_defaults = { 131 .rob_buffer_size_in_kbyte = 64, 132 .det_buffer_size_in_kbyte = 164, 133 .dpp_output_buffer_pixels = 2560, 134 .opp_output_buffer_lines = 1, 135 .pixel_chunk_size_in_kbyte = 8, 136 .pte_enable = dcn_bw_yes, 137 .pte_chunk_size = 2, /*kbytes*/ 138 .meta_chunk_size = 2, /*kbytes*/ 139 .writeback_chunk_size = 2, /*kbytes*/ 140 .odm_capability = dcn_bw_no, 141 .dsc_capability = dcn_bw_no, 142 .line_buffer_size = 589824, /*bit*/ 143 .max_line_buffer_lines = 12, 144 .is_line_buffer_bpp_fixed = dcn_bw_no, 145 .line_buffer_fixed_bpp = dcn_bw_na, 146 .writeback_luma_buffer_size = 12, /*kbytes*/ 147 .writeback_chroma_buffer_size = 8, /*kbytes*/ 148 .max_num_dpp = 4, 149 .max_num_writeback = 2, 150 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/ 151 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/ 152 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/ 153 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/ 154 .max_hscl_ratio = 4, 155 .max_vscl_ratio = 4, 156 .max_hscl_taps = 8, 157 .max_vscl_taps = 8, 158 .pte_buffer_size_in_requests = 42, 159 .dispclk_ramping_margin = 1, /*%*/ 160 .under_scan_factor = 1.11f, 161 .max_inter_dcn_tile_repeaters = 8, 162 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no, 163 .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no, 164 .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/ 165 }; 166 167 static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode) 168 { 169 switch (sw_mode) { 170 case DC_SW_LINEAR: 171 return dcn_bw_sw_linear; 172 case DC_SW_4KB_S: 173 return dcn_bw_sw_4_kb_s; 174 case DC_SW_4KB_D: 175 return dcn_bw_sw_4_kb_d; 176 case DC_SW_64KB_S: 177 return dcn_bw_sw_64_kb_s; 178 case DC_SW_64KB_D: 179 return dcn_bw_sw_64_kb_d; 180 case DC_SW_VAR_S: 181 return dcn_bw_sw_var_s; 182 case DC_SW_VAR_D: 183 return dcn_bw_sw_var_d; 184 case DC_SW_64KB_S_T: 185 return dcn_bw_sw_64_kb_s_t; 186 case DC_SW_64KB_D_T: 187 return dcn_bw_sw_64_kb_d_t; 188 case DC_SW_4KB_S_X: 189 return dcn_bw_sw_4_kb_s_x; 190 case DC_SW_4KB_D_X: 191 return dcn_bw_sw_4_kb_d_x; 192 case DC_SW_64KB_S_X: 193 return dcn_bw_sw_64_kb_s_x; 194 case DC_SW_64KB_D_X: 195 return dcn_bw_sw_64_kb_d_x; 196 case DC_SW_VAR_S_X: 197 return dcn_bw_sw_var_s_x; 198 case DC_SW_VAR_D_X: 199 return dcn_bw_sw_var_d_x; 200 case DC_SW_256B_S: 201 case DC_SW_256_D: 202 case DC_SW_256_R: 203 case DC_SW_4KB_R: 204 case DC_SW_64KB_R: 205 case DC_SW_VAR_R: 206 case DC_SW_4KB_R_X: 207 case DC_SW_64KB_R_X: 208 case DC_SW_VAR_R_X: 209 default: 210 BREAK_TO_DEBUGGER(); /*not in formula*/ 211 return dcn_bw_sw_4_kb_s; 212 } 213 } 214 215 static int tl_lb_bpp_to_int(enum lb_pixel_depth depth) 216 { 217 switch (depth) { 218 case LB_PIXEL_DEPTH_18BPP: 219 return 18; 220 case LB_PIXEL_DEPTH_24BPP: 221 return 24; 222 case LB_PIXEL_DEPTH_30BPP: 223 return 30; 224 case LB_PIXEL_DEPTH_36BPP: 225 return 36; 226 default: 227 return 30; 228 } 229 } 230 231 static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format) 232 { 233 switch (format) { 234 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 235 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 236 return dcn_bw_rgb_sub_16; 237 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 238 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 239 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 240 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 241 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 242 return dcn_bw_rgb_sub_32; 243 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 244 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 245 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 246 return dcn_bw_rgb_sub_64; 247 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 248 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 249 return dcn_bw_yuv420_sub_8; 250 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 251 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 252 return dcn_bw_yuv420_sub_10; 253 default: 254 return dcn_bw_rgb_sub_32; 255 } 256 } 257 258 enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode) 259 { 260 switch (sw_mode) { 261 /* for 4/8/16 high tiles */ 262 case DC_SW_LINEAR: 263 return dm_4k_tile; 264 case DC_SW_4KB_S: 265 case DC_SW_4KB_S_X: 266 return dm_4k_tile; 267 case DC_SW_64KB_S: 268 case DC_SW_64KB_S_X: 269 case DC_SW_64KB_S_T: 270 return dm_64k_tile; 271 case DC_SW_VAR_S: 272 case DC_SW_VAR_S_X: 273 return dm_256k_tile; 274 275 /* For 64bpp 2 high tiles */ 276 case DC_SW_4KB_D: 277 case DC_SW_4KB_D_X: 278 return dm_4k_tile; 279 case DC_SW_64KB_D: 280 case DC_SW_64KB_D_X: 281 case DC_SW_64KB_D_T: 282 return dm_64k_tile; 283 case DC_SW_VAR_D: 284 case DC_SW_VAR_D_X: 285 return dm_256k_tile; 286 287 case DC_SW_4KB_R: 288 case DC_SW_4KB_R_X: 289 return dm_4k_tile; 290 case DC_SW_64KB_R: 291 case DC_SW_64KB_R_X: 292 return dm_64k_tile; 293 case DC_SW_VAR_R: 294 case DC_SW_VAR_R_X: 295 return dm_256k_tile; 296 297 /* Unsupported swizzle modes for dcn */ 298 case DC_SW_256B_S: 299 default: 300 ASSERT(0); /* Not supported */ 301 return 0; 302 } 303 } 304 305 static void pipe_ctx_to_e2e_pipe_params ( 306 const struct pipe_ctx *pipe, 307 struct _vcs_dpi_display_pipe_params_st *input) 308 { 309 input->src.is_hsplit = false; 310 if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) 311 input->src.is_hsplit = true; 312 else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) 313 input->src.is_hsplit = true; 314 315 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { 316 /* 317 * this method requires us to always re-calculate watermark when dcc change 318 * between flip. 319 */ 320 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0; 321 } else { 322 /* 323 * allow us to disable dcc on the fly without re-calculating WM 324 * 325 * extra overhead for DCC is quite small. for 1080p WM without 326 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us) 327 */ 328 unsigned int bpe; 329 330 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> 331 dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0; 332 } 333 input->src.dcc_rate = 1; 334 input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch; 335 input->src.source_scan = dm_horz; 336 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; 337 338 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; 339 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; 340 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; 341 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; 342 input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */ 343 input->src.cur0_bpp = 32; 344 345 input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle); 346 347 switch (pipe->plane_state->rotation) { 348 case ROTATION_ANGLE_0: 349 case ROTATION_ANGLE_180: 350 input->src.source_scan = dm_horz; 351 break; 352 case ROTATION_ANGLE_90: 353 case ROTATION_ANGLE_270: 354 input->src.source_scan = dm_vert; 355 break; 356 default: 357 ASSERT(0); /* Not supported */ 358 break; 359 } 360 361 /* TODO: Fix pixel format mappings */ 362 switch (pipe->plane_state->format) { 363 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 364 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 365 input->src.source_format = dm_420_8; 366 input->src.viewport_width_c = input->src.viewport_width / 2; 367 input->src.viewport_height_c = input->src.viewport_height / 2; 368 break; 369 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 370 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 371 input->src.source_format = dm_420_10; 372 input->src.viewport_width_c = input->src.viewport_width / 2; 373 input->src.viewport_height_c = input->src.viewport_height / 2; 374 break; 375 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 376 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 377 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 378 input->src.source_format = dm_444_64; 379 input->src.viewport_width_c = input->src.viewport_width; 380 input->src.viewport_height_c = input->src.viewport_height; 381 break; 382 default: 383 input->src.source_format = dm_444_32; 384 input->src.viewport_width_c = input->src.viewport_width; 385 input->src.viewport_height_c = input->src.viewport_height; 386 break; 387 } 388 389 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; 390 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; 391 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; 392 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; 393 if (input->scale_ratio_depth.vinit < 1.0) 394 input->scale_ratio_depth.vinit = 1; 395 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; 396 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; 397 input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c; 398 input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0; 399 input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0; 400 input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0; 401 if (input->scale_ratio_depth.vinit_c < 1.0) 402 input->scale_ratio_depth.vinit_c = 1; 403 switch (pipe->plane_res.scl_data.lb_params.depth) { 404 case LB_PIXEL_DEPTH_30BPP: 405 input->scale_ratio_depth.lb_depth = 30; break; 406 case LB_PIXEL_DEPTH_36BPP: 407 input->scale_ratio_depth.lb_depth = 36; break; 408 default: 409 input->scale_ratio_depth.lb_depth = 24; break; 410 } 411 412 413 input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top 414 + pipe->stream->timing.v_border_bottom; 415 416 input->dest.recout_width = pipe->plane_res.scl_data.recout.width; 417 input->dest.recout_height = pipe->plane_res.scl_data.recout.height; 418 419 input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width; 420 input->dest.full_recout_height = pipe->plane_res.scl_data.recout.height; 421 422 input->dest.htotal = pipe->stream->timing.h_total; 423 input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch; 424 input->dest.hblank_end = input->dest.hblank_start 425 - pipe->stream->timing.h_addressable 426 - pipe->stream->timing.h_border_left 427 - pipe->stream->timing.h_border_right; 428 429 input->dest.vtotal = pipe->stream->timing.v_total; 430 input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch; 431 input->dest.vblank_end = input->dest.vblank_start 432 - pipe->stream->timing.v_addressable 433 - pipe->stream->timing.v_border_bottom 434 - pipe->stream->timing.v_border_top; 435 input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0; 436 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; 437 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; 438 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; 439 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width; 440 441 } 442 443 static void dcn_bw_calc_rq_dlg_ttu( 444 const struct dc *dc, 445 const struct dcn_bw_internal_vars *v, 446 struct pipe_ctx *pipe, 447 int in_idx) 448 { 449 struct display_mode_lib *dml = (struct display_mode_lib *)__UNCONST(&dc->dml); 450 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs; 451 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs; 452 struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs; 453 struct _vcs_dpi_display_rq_params_st rq_param = {0}; 454 struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0}; 455 struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } }; 456 float total_active_bw = 0; 457 float total_prefetch_bw = 0; 458 int total_flip_bytes = 0; 459 int i; 460 461 memset(dlg_regs, 0, sizeof(*dlg_regs)); 462 memset(ttu_regs, 0, sizeof(*ttu_regs)); 463 memset(rq_regs, 0, sizeof(*rq_regs)); 464 465 for (i = 0; i < number_of_planes; i++) { 466 total_active_bw += v->read_bandwidth[i]; 467 total_prefetch_bw += v->prefetch_bandwidth[i]; 468 total_flip_bytes += v->total_immediate_flip_bytes[i]; 469 } 470 dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw); 471 if (dlg_sys_param.total_flip_bw < 0.0) 472 dlg_sys_param.total_flip_bw = 0; 473 474 dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark; 475 dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark; 476 dlg_sys_param.t_urg_wm_us = v->urgent_watermark; 477 dlg_sys_param.t_extra_us = v->urgent_extra_latency; 478 dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep; 479 dlg_sys_param.total_flip_bytes = total_flip_bytes; 480 481 pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe); 482 input.clks_cfg.dcfclk_mhz = v->dcfclk; 483 input.clks_cfg.dispclk_mhz = v->dispclk; 484 input.clks_cfg.dppclk_mhz = v->dppclk; 485 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 486 input.clks_cfg.socclk_mhz = v->socclk; 487 input.clks_cfg.voltage = v->voltage_level; 488 // dc->dml.logger = pool->base.logger; 489 input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444; 490 input.dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp; 491 //input[in_idx].dout.output_standard; 492 493 /*todo: soc->sr_enter_plus_exit_time??*/ 494 dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep; 495 496 dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src); 497 dml1_extract_rq_regs(dml, rq_regs, rq_param); 498 dml1_rq_dlg_get_dlg_params( 499 dml, 500 dlg_regs, 501 ttu_regs, 502 rq_param.dlg, 503 dlg_sys_param, 504 input, 505 true, 506 true, 507 v->pte_enable == dcn_bw_yes, 508 pipe->plane_state->flip_immediate); 509 } 510 511 static void split_stream_across_pipes( 512 struct resource_context *res_ctx, 513 const struct resource_pool *pool, 514 struct pipe_ctx *primary_pipe, 515 struct pipe_ctx *secondary_pipe) 516 { 517 int pipe_idx = secondary_pipe->pipe_idx; 518 519 if (!primary_pipe->plane_state) 520 return; 521 522 *secondary_pipe = *primary_pipe; 523 524 secondary_pipe->pipe_idx = pipe_idx; 525 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; 526 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; 527 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; 528 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; 529 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; 530 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; 531 if (primary_pipe->bottom_pipe) { 532 ASSERT(primary_pipe->bottom_pipe != secondary_pipe); 533 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; 534 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; 535 } 536 primary_pipe->bottom_pipe = secondary_pipe; 537 secondary_pipe->top_pipe = primary_pipe; 538 539 resource_build_scaling_params(primary_pipe); 540 resource_build_scaling_params(secondary_pipe); 541 } 542 543 #if 0 544 static void calc_wm_sets_and_perf_params( 545 struct dc_state *context, 546 struct dcn_bw_internal_vars *v) 547 { 548 /* Calculate set A last to keep internal var state consistent for required config */ 549 if (v->voltage_level < 2) { 550 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8; 551 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8; 552 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8; 553 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); 554 555 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = 556 v->stutter_exit_watermark * 1000; 557 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = 558 v->stutter_enter_plus_exit_watermark * 1000; 559 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = 560 v->dram_clock_change_watermark * 1000; 561 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 562 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000; 563 564 v->dcfclk_per_state[1] = v->dcfclkv_nom0p8; 565 v->dcfclk_per_state[0] = v->dcfclkv_nom0p8; 566 v->dcfclk = v->dcfclkv_nom0p8; 567 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); 568 569 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = 570 v->stutter_exit_watermark * 1000; 571 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = 572 v->stutter_enter_plus_exit_watermark * 1000; 573 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = 574 v->dram_clock_change_watermark * 1000; 575 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 576 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000; 577 } 578 579 if (v->voltage_level < 3) { 580 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9; 581 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9; 582 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9; 583 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9; 584 v->dcfclk_per_state[2] = v->dcfclkv_max0p9; 585 v->dcfclk_per_state[1] = v->dcfclkv_max0p9; 586 v->dcfclk_per_state[0] = v->dcfclkv_max0p9; 587 v->dcfclk = v->dcfclkv_max0p9; 588 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); 589 590 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = 591 v->stutter_exit_watermark * 1000; 592 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = 593 v->stutter_enter_plus_exit_watermark * 1000; 594 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = 595 v->dram_clock_change_watermark * 1000; 596 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 597 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000; 598 } 599 600 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8; 601 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72; 602 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65; 603 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level]; 604 v->dcfclk_per_state[2] = v->dcfclkv_nom0p8; 605 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72; 606 v->dcfclk_per_state[0] = v->dcfclkv_min0p65; 607 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; 608 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); 609 610 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = 611 v->stutter_exit_watermark * 1000; 612 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = 613 v->stutter_enter_plus_exit_watermark * 1000; 614 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 615 v->dram_clock_change_watermark * 1000; 616 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 617 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000; 618 if (v->voltage_level >= 2) { 619 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; 620 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; 621 } 622 if (v->voltage_level >= 3) 623 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 624 } 625 #endif 626 627 static bool dcn_bw_apply_registry_override(struct dc *dc) 628 { 629 volatile bool updated = false; 630 631 DC_FP_START(); 632 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns 633 && dc->debug.sr_exit_time_ns) { 634 updated = true; 635 dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0; 636 } 637 638 if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000) 639 != dc->debug.sr_enter_plus_exit_time_ns 640 && dc->debug.sr_enter_plus_exit_time_ns) { 641 updated = true; 642 dc->dcn_soc->sr_enter_plus_exit_time = 643 dc->debug.sr_enter_plus_exit_time_ns / 1000.0; 644 } 645 646 if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns 647 && dc->debug.urgent_latency_ns) { 648 updated = true; 649 dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0; 650 } 651 652 if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000) 653 != dc->debug.percent_of_ideal_drambw 654 && dc->debug.percent_of_ideal_drambw) { 655 updated = true; 656 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency = 657 dc->debug.percent_of_ideal_drambw; 658 } 659 660 if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000) 661 != dc->debug.dram_clock_change_latency_ns 662 && dc->debug.dram_clock_change_latency_ns) { 663 updated = true; 664 dc->dcn_soc->dram_clock_change_latency = 665 dc->debug.dram_clock_change_latency_ns / 1000.0; 666 } 667 DC_FP_END(); 668 669 return updated; 670 } 671 672 static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v) 673 { 674 /* 675 * disable optional pipe split by lower dispclk bounding box 676 * at DPM0 677 */ 678 v->max_dispclk[0] = v->max_dppclk_vmin0p65; 679 } 680 681 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v, 682 unsigned int pixel_rate_100hz) 683 { 684 float pixel_rate_mhz = pixel_rate_100hz / 10000; 685 686 /* 687 * force enabling pipe split by lower dpp clock for DPM0 to just 688 * below the specify pixel_rate, so bw calc would split pipe. 689 */ 690 if (pixel_rate_mhz < v->max_dppclk[0]) 691 v->max_dppclk[0] = pixel_rate_mhz; 692 } 693 694 static void hack_bounding_box(struct dcn_bw_internal_vars *v, 695 struct dc_debug_options *dbg, 696 struct dc_state *context) 697 { 698 if (dbg->pipe_split_policy == MPC_SPLIT_AVOID) 699 hack_disable_optional_pipe_split(v); 700 701 if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP && 702 context->stream_count >= 2) 703 hack_disable_optional_pipe_split(v); 704 705 if (context->stream_count == 1 && 706 dbg->force_single_disp_pipe_split) 707 hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz); 708 } 709 710 711 unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev) 712 { 713 /* for dali & pollock, the highest voltage level we want is 0 */ 714 if (ASICREV_IS_POLLOCK(hw_internal_rev) || ASICREV_IS_DALI(hw_internal_rev)) 715 return 0; 716 717 /* we are ok with all levels */ 718 return 4; 719 } 720 721 bool dcn_validate_bandwidth( 722 struct dc *dc, 723 struct dc_state *context, 724 bool fast_validate) 725 { 726 /* 727 * we want a breakdown of the various stages of validation, which the 728 * perf_trace macro doesn't support 729 */ 730 BW_VAL_TRACE_SETUP(); 731 732 const struct resource_pool *pool = dc->res_pool; 733 struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; 734 int i, input_idx, k; 735 int vesa_sync_start, asic_blank_end, asic_blank_start; 736 volatile bool bw_limit_pass; 737 float bw_limit; 738 739 PERFORMANCE_TRACE_START(); 740 741 BW_VAL_TRACE_COUNT(); 742 743 if (dcn_bw_apply_registry_override(dc)) 744 dcn_bw_sync_calcs_and_dml(dc); 745 746 memset(v, 0, sizeof(*v)); 747 DC_FP_START(); 748 749 v->sr_exit_time = dc->dcn_soc->sr_exit_time; 750 v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time; 751 v->urgent_latency = dc->dcn_soc->urgent_latency; 752 v->write_back_latency = dc->dcn_soc->write_back_latency; 753 v->percent_of_ideal_drambw_received_after_urg_latency = 754 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency; 755 756 v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65; 757 v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72; 758 v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8; 759 v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9; 760 761 v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65; 762 v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72; 763 v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8; 764 v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9; 765 766 v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65; 767 v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72; 768 v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8; 769 v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9; 770 771 v->socclk = dc->dcn_soc->socclk; 772 773 v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65; 774 v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72; 775 v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8; 776 v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9; 777 778 v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65; 779 v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72; 780 v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8; 781 v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9; 782 783 v->downspreading = dc->dcn_soc->downspreading; 784 v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles; 785 v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel; 786 v->number_of_channels = dc->dcn_soc->number_of_channels; 787 v->vmm_page_size = dc->dcn_soc->vmm_page_size; 788 v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency; 789 v->return_bus_width = dc->dcn_soc->return_bus_width; 790 791 v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte; 792 v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte; 793 v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels; 794 v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines; 795 v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte; 796 v->pte_enable = dc->dcn_ip->pte_enable; 797 v->pte_chunk_size = dc->dcn_ip->pte_chunk_size; 798 v->meta_chunk_size = dc->dcn_ip->meta_chunk_size; 799 v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size; 800 v->odm_capability = dc->dcn_ip->odm_capability; 801 v->dsc_capability = dc->dcn_ip->dsc_capability; 802 v->line_buffer_size = dc->dcn_ip->line_buffer_size; 803 v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed; 804 v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp; 805 v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines; 806 v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size; 807 v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size; 808 v->max_num_dpp = dc->dcn_ip->max_num_dpp; 809 v->max_num_writeback = dc->dcn_ip->max_num_writeback; 810 v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput; 811 v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput; 812 v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput; 813 v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput; 814 v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio; 815 v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio; 816 v->max_hscl_taps = dc->dcn_ip->max_hscl_taps; 817 v->max_vscl_taps = dc->dcn_ip->max_vscl_taps; 818 v->under_scan_factor = dc->dcn_ip->under_scan_factor; 819 v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests; 820 v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin; 821 v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters; 822 v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 823 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 824 v->bug_forcing_luma_and_chroma_request_to_same_size_fixed = 825 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed; 826 827 v->voltage[5] = dcn_bw_no_support; 828 v->voltage[4] = dcn_bw_v_max0p9; 829 v->voltage[3] = dcn_bw_v_max0p9; 830 v->voltage[2] = dcn_bw_v_nom0p8; 831 v->voltage[1] = dcn_bw_v_mid0p72; 832 v->voltage[0] = dcn_bw_v_min0p65; 833 v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9; 834 v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9; 835 v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9; 836 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8; 837 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72; 838 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65; 839 v->dcfclk_per_state[5] = v->dcfclkv_max0p9; 840 v->dcfclk_per_state[4] = v->dcfclkv_max0p9; 841 v->dcfclk_per_state[3] = v->dcfclkv_max0p9; 842 v->dcfclk_per_state[2] = v->dcfclkv_nom0p8; 843 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72; 844 v->dcfclk_per_state[0] = v->dcfclkv_min0p65; 845 v->max_dispclk[5] = v->max_dispclk_vmax0p9; 846 v->max_dispclk[4] = v->max_dispclk_vmax0p9; 847 v->max_dispclk[3] = v->max_dispclk_vmax0p9; 848 v->max_dispclk[2] = v->max_dispclk_vnom0p8; 849 v->max_dispclk[1] = v->max_dispclk_vmid0p72; 850 v->max_dispclk[0] = v->max_dispclk_vmin0p65; 851 v->max_dppclk[5] = v->max_dppclk_vmax0p9; 852 v->max_dppclk[4] = v->max_dppclk_vmax0p9; 853 v->max_dppclk[3] = v->max_dppclk_vmax0p9; 854 v->max_dppclk[2] = v->max_dppclk_vnom0p8; 855 v->max_dppclk[1] = v->max_dppclk_vmid0p72; 856 v->max_dppclk[0] = v->max_dppclk_vmin0p65; 857 v->phyclk_per_state[5] = v->phyclkv_max0p9; 858 v->phyclk_per_state[4] = v->phyclkv_max0p9; 859 v->phyclk_per_state[3] = v->phyclkv_max0p9; 860 v->phyclk_per_state[2] = v->phyclkv_nom0p8; 861 v->phyclk_per_state[1] = v->phyclkv_mid0p72; 862 v->phyclk_per_state[0] = v->phyclkv_min0p65; 863 v->synchronized_vblank = dcn_bw_no; 864 v->ta_pscalculation = dcn_bw_override; 865 v->allow_different_hratio_vratio = dcn_bw_yes; 866 867 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { 868 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 869 870 if (!pipe->stream) 871 continue; 872 /* skip all but first of split pipes */ 873 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) 874 continue; 875 876 v->underscan_output[input_idx] = false; /* taken care of in recout already*/ 877 v->interlace_output[input_idx] = false; 878 879 v->htotal[input_idx] = pipe->stream->timing.h_total; 880 v->vtotal[input_idx] = pipe->stream->timing.v_total; 881 v->vactive[input_idx] = pipe->stream->timing.v_addressable + 882 pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom; 883 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total 884 - v->vactive[input_idx] 885 - pipe->stream->timing.v_front_porch; 886 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0; 887 if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 888 v->pixel_clock[input_idx] *= 2; 889 if (!pipe->plane_state) { 890 v->dcc_enable[input_idx] = dcn_bw_yes; 891 v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; 892 v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; 893 v->lb_bit_per_pixel[input_idx] = 30; 894 v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; 895 v->viewport_height[input_idx] = pipe->stream->timing.v_addressable; 896 /* 897 * for cases where we have no plane, we want to validate up to 1080p 898 * source size because here we are only interested in if the output 899 * timing is supported or not. if we cannot support native resolution 900 * of the high res display, we still want to support lower res up scale 901 * to native 902 */ 903 if (v->viewport_width[input_idx] > 1920) 904 v->viewport_width[input_idx] = 1920; 905 if (v->viewport_height[input_idx] > 1080) 906 v->viewport_height[input_idx] = 1080; 907 v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx]; 908 v->scaler_recout_height[input_idx] = v->viewport_height[input_idx]; 909 v->override_hta_ps[input_idx] = 1; 910 v->override_vta_ps[input_idx] = 1; 911 v->override_hta_pschroma[input_idx] = 1; 912 v->override_vta_pschroma[input_idx] = 1; 913 v->source_scan[input_idx] = dcn_bw_hor; 914 915 } else { 916 v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height; 917 v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width; 918 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width; 919 v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height; 920 if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) { 921 if (pipe->plane_state->rotation % 2 == 0) { 922 int viewport_end = pipe->plane_res.scl_data.viewport.width 923 + pipe->plane_res.scl_data.viewport.x; 924 int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width 925 + pipe->bottom_pipe->plane_res.scl_data.viewport.x; 926 927 if (viewport_end > viewport_b_end) 928 v->viewport_width[input_idx] = viewport_end 929 - pipe->bottom_pipe->plane_res.scl_data.viewport.x; 930 else 931 v->viewport_width[input_idx] = viewport_b_end 932 - pipe->plane_res.scl_data.viewport.x; 933 } else { 934 int viewport_end = pipe->plane_res.scl_data.viewport.height 935 + pipe->plane_res.scl_data.viewport.y; 936 int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height 937 + pipe->bottom_pipe->plane_res.scl_data.viewport.y; 938 939 if (viewport_end > viewport_b_end) 940 v->viewport_height[input_idx] = viewport_end 941 - pipe->bottom_pipe->plane_res.scl_data.viewport.y; 942 else 943 v->viewport_height[input_idx] = viewport_b_end 944 - pipe->plane_res.scl_data.viewport.y; 945 } 946 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width 947 + pipe->bottom_pipe->plane_res.scl_data.recout.width; 948 } 949 950 if (pipe->plane_state->rotation % 2 == 0) { 951 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value 952 || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]); 953 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value 954 || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]); 955 } else { 956 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value 957 || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]); 958 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value 959 || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]); 960 } 961 962 if (dc->debug.optimized_watermark) { 963 /* 964 * this method requires us to always re-calculate watermark when dcc change 965 * between flip. 966 */ 967 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; 968 } else { 969 /* 970 * allow us to disable dcc on the fly without re-calculating WM 971 * 972 * extra overhead for DCC is quite small. for 1080p WM without 973 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us) 974 */ 975 unsigned int bpe; 976 977 v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format( 978 pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no; 979 } 980 981 v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( 982 pipe->plane_state->format); 983 v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( 984 pipe->plane_state->tiling_info.gfx9.swizzle); 985 v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); 986 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; 987 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; 988 v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; 989 v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; 990 /* 991 * Spreadsheet doesn't handle taps_c is one properly, 992 * need to force Chroma to always be scaled to pass 993 * bandwidth validation. 994 */ 995 if (v->override_hta_pschroma[input_idx] == 1) 996 v->override_hta_pschroma[input_idx] = 2; 997 if (v->override_vta_pschroma[input_idx] == 1) 998 v->override_vta_pschroma[input_idx] = 2; 999 v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; 1000 } 1001 if (v->is_line_buffer_bpp_fixed == dcn_bw_yes) 1002 v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp; 1003 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/ 1004 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding == 1005 PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444; 1006 v->output[input_idx] = pipe->stream->signal == 1007 SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp; 1008 v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc; 1009 if (v->output[input_idx] == dcn_bw_hdmi) { 1010 switch (pipe->stream->timing.display_color_depth) { 1011 case COLOR_DEPTH_101010: 1012 v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc; 1013 break; 1014 case COLOR_DEPTH_121212: 1015 v->output_deep_color[input_idx] = dcn_bw_encoder_12bpc; 1016 break; 1017 case COLOR_DEPTH_161616: 1018 v->output_deep_color[input_idx] = dcn_bw_encoder_16bpc; 1019 break; 1020 default: 1021 break; 1022 } 1023 } 1024 1025 input_idx++; 1026 } 1027 v->number_of_active_planes = input_idx; 1028 1029 scaler_settings_calculation(v); 1030 1031 hack_bounding_box(v, &dc->debug, context); 1032 1033 mode_support_and_system_configuration(v); 1034 1035 /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */ 1036 if (v->voltage_level != 0 1037 && context->stream_count == 1 1038 && dc->debug.force_single_disp_pipe_split) { 1039 v->max_dppclk[0] = v->max_dppclk_vmin0p65; 1040 mode_support_and_system_configuration(v); 1041 } 1042 1043 if (v->voltage_level == 0 && 1044 (dc->debug.sr_exit_time_dpm0_ns 1045 || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) { 1046 1047 if (dc->debug.sr_enter_plus_exit_time_dpm0_ns) 1048 v->sr_enter_plus_exit_time = 1049 dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; 1050 if (dc->debug.sr_exit_time_dpm0_ns) 1051 v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f; 1052 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; 1053 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time; 1054 mode_support_and_system_configuration(v); 1055 } 1056 1057 display_pipe_configuration(v); 1058 1059 for (k = 0; k <= v->number_of_active_planes - 1; k++) { 1060 if (v->source_scan[k] == dcn_bw_hor) 1061 v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k]; 1062 else 1063 v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k]; 1064 } 1065 for (k = 0; k <= v->number_of_active_planes - 1; k++) { 1066 if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { 1067 v->byte_per_pixel_dety[k] = 8.0; 1068 v->byte_per_pixel_detc[k] = 0.0; 1069 } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { 1070 v->byte_per_pixel_dety[k] = 4.0; 1071 v->byte_per_pixel_detc[k] = 0.0; 1072 } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { 1073 v->byte_per_pixel_dety[k] = 2.0; 1074 v->byte_per_pixel_detc[k] = 0.0; 1075 } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { 1076 v->byte_per_pixel_dety[k] = 1.0; 1077 v->byte_per_pixel_detc[k] = 2.0; 1078 } else { 1079 v->byte_per_pixel_dety[k] = 4.0f / 3.0f; 1080 v->byte_per_pixel_detc[k] = 8.0f / 3.0f; 1081 } 1082 } 1083 1084 v->total_data_read_bandwidth = 0.0; 1085 for (k = 0; k <= v->number_of_active_planes - 1; k++) { 1086 v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] * 1087 dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; 1088 v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] * 1089 dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0; 1090 v->total_data_read_bandwidth = v->total_data_read_bandwidth + 1091 v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k]; 1092 } 1093 1094 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1095 1096 if (v->voltage_level != number_of_states_plus_one && !fast_validate) { 1097 float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second; 1098 1099 if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65) 1100 bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65; 1101 else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72) 1102 bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72; 1103 else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8) 1104 bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8; 1105 else 1106 bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9; 1107 1108 if (bw_consumed < v->fabric_and_dram_bandwidth) 1109 if (dc->debug.voltage_align_fclk) 1110 bw_consumed = v->fabric_and_dram_bandwidth; 1111 1112 display_pipe_configuration(v); 1113 /*calc_wm_sets_and_perf_params(context, v);*/ 1114 /* Only 1 set is used by dcn since no noticeable 1115 * performance improvement was measured and due to hw bug DEGVIDCN10-254 1116 */ 1117 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); 1118 1119 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = 1120 v->stutter_exit_watermark * 1000; 1121 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = 1122 v->stutter_enter_plus_exit_watermark * 1000; 1123 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 1124 v->dram_clock_change_watermark * 1000; 1125 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 1126 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000; 1127 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; 1128 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; 1129 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; 1130 1131 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 1132 (ddr4_dram_factor_single_Channel * v->number_of_channels)); 1133 if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) 1134 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32); 1135 1136 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); 1137 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000); 1138 1139 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000); 1140 if (dc->debug.max_disp_clk == true) 1141 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); 1142 1143 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < 1144 dc->debug.min_disp_clk_khz) { 1145 context->bw_ctx.bw.dcn.clk.dispclk_khz = 1146 dc->debug.min_disp_clk_khz; 1147 } 1148 1149 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / 1150 v->dispclk_dppclk_ratio; 1151 context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level]; 1152 switch (v->voltage_level) { 1153 case 0: 1154 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = 1155 (int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000); 1156 break; 1157 case 1: 1158 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = 1159 (int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000); 1160 break; 1161 case 2: 1162 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = 1163 (int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000); 1164 break; 1165 default: 1166 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = 1167 (int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000); 1168 break; 1169 } 1170 1171 BW_VAL_TRACE_END_WATERMARKS(); 1172 1173 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { 1174 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1175 1176 /* skip inactive pipe */ 1177 if (!pipe->stream) 1178 continue; 1179 /* skip all but first of split pipes */ 1180 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) 1181 continue; 1182 1183 pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; 1184 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; 1185 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; 1186 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; 1187 1188 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; 1189 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; 1190 vesa_sync_start = pipe->stream->timing.v_addressable + 1191 pipe->stream->timing.v_border_bottom + 1192 pipe->stream->timing.v_front_porch; 1193 1194 asic_blank_end = (pipe->stream->timing.v_total - 1195 vesa_sync_start - 1196 pipe->stream->timing.v_border_top) 1197 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); 1198 1199 asic_blank_start = asic_blank_end + 1200 (pipe->stream->timing.v_border_top + 1201 pipe->stream->timing.v_addressable + 1202 pipe->stream->timing.v_border_bottom) 1203 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); 1204 1205 pipe->pipe_dlg_param.vblank_start = asic_blank_start; 1206 pipe->pipe_dlg_param.vblank_end = asic_blank_end; 1207 1208 if (pipe->plane_state) { 1209 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 1210 1211 pipe->plane_state->update_flags.bits.full_update = 1; 1212 1213 if (v->dpp_per_plane[input_idx] == 2 || 1214 ((pipe->stream->view_format == 1215 VIEW_3D_FORMAT_SIDE_BY_SIDE || 1216 pipe->stream->view_format == 1217 VIEW_3D_FORMAT_TOP_AND_BOTTOM) && 1218 (pipe->stream->timing.timing_3d_format == 1219 TIMING_3D_FORMAT_TOP_AND_BOTTOM || 1220 pipe->stream->timing.timing_3d_format == 1221 TIMING_3D_FORMAT_SIDE_BY_SIDE))) { 1222 if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 1223 /* update previously split pipe */ 1224 hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; 1225 hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; 1226 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; 1227 hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; 1228 1229 hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; 1230 hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; 1231 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start; 1232 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end; 1233 } else { 1234 /* pipe not split previously needs split */ 1235 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe); 1236 ASSERT(hsplit_pipe); 1237 split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe); 1238 } 1239 1240 dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx); 1241 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 1242 /* merge previously split pipe */ 1243 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; 1244 if (hsplit_pipe->bottom_pipe) 1245 hsplit_pipe->bottom_pipe->top_pipe = pipe; 1246 hsplit_pipe->plane_state = NULL; 1247 hsplit_pipe->stream = NULL; 1248 hsplit_pipe->top_pipe = NULL; 1249 hsplit_pipe->bottom_pipe = NULL; 1250 /* Clear plane_res and stream_res */ 1251 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); 1252 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); 1253 resource_build_scaling_params(pipe); 1254 } 1255 /* for now important to do this after pipe split for building e2e params */ 1256 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx); 1257 } 1258 1259 input_idx++; 1260 } 1261 } else if (v->voltage_level == number_of_states_plus_one) { 1262 BW_VAL_TRACE_SKIP(fail); 1263 } else if (fast_validate) { 1264 BW_VAL_TRACE_SKIP(fast); 1265 } 1266 1267 if (v->voltage_level == 0) { 1268 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = 1269 dc->dcn_soc->sr_enter_plus_exit_time; 1270 context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; 1271 } 1272 1273 /* 1274 * BW limit is set to prevent display from impacting other system functions 1275 */ 1276 1277 bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9; 1278 bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit; 1279 1280 DC_FP_END(); 1281 1282 PERFORMANCE_TRACE_END(); 1283 BW_VAL_TRACE_FINISH(); 1284 1285 if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev)) 1286 return true; 1287 else 1288 return false; 1289 } 1290 1291 static unsigned int dcn_find_normalized_clock_vdd_Level( 1292 const struct dc *dc, 1293 enum dm_pp_clock_type clocks_type, 1294 int clocks_in_khz) 1295 { 1296 int vdd_level = dcn_bw_v_min0p65; 1297 1298 if (clocks_in_khz == 0)/*todo some clock not in the considerations*/ 1299 return vdd_level; 1300 1301 switch (clocks_type) { 1302 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 1303 if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) { 1304 vdd_level = dcn_bw_v_max0p91; 1305 BREAK_TO_DEBUGGER(); 1306 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) { 1307 vdd_level = dcn_bw_v_max0p9; 1308 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) { 1309 vdd_level = dcn_bw_v_nom0p8; 1310 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) { 1311 vdd_level = dcn_bw_v_mid0p72; 1312 } else 1313 vdd_level = dcn_bw_v_min0p65; 1314 break; 1315 case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: 1316 if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) { 1317 vdd_level = dcn_bw_v_max0p91; 1318 BREAK_TO_DEBUGGER(); 1319 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) { 1320 vdd_level = dcn_bw_v_max0p9; 1321 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) { 1322 vdd_level = dcn_bw_v_nom0p8; 1323 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) { 1324 vdd_level = dcn_bw_v_mid0p72; 1325 } else 1326 vdd_level = dcn_bw_v_min0p65; 1327 break; 1328 1329 case DM_PP_CLOCK_TYPE_DPPCLK: 1330 if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) { 1331 vdd_level = dcn_bw_v_max0p91; 1332 BREAK_TO_DEBUGGER(); 1333 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) { 1334 vdd_level = dcn_bw_v_max0p9; 1335 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) { 1336 vdd_level = dcn_bw_v_nom0p8; 1337 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) { 1338 vdd_level = dcn_bw_v_mid0p72; 1339 } else 1340 vdd_level = dcn_bw_v_min0p65; 1341 break; 1342 1343 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 1344 { 1345 unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels); 1346 1347 if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) { 1348 vdd_level = dcn_bw_v_max0p91; 1349 BREAK_TO_DEBUGGER(); 1350 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) { 1351 vdd_level = dcn_bw_v_max0p9; 1352 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) { 1353 vdd_level = dcn_bw_v_nom0p8; 1354 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) { 1355 vdd_level = dcn_bw_v_mid0p72; 1356 } else 1357 vdd_level = dcn_bw_v_min0p65; 1358 } 1359 break; 1360 1361 case DM_PP_CLOCK_TYPE_DCFCLK: 1362 if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) { 1363 vdd_level = dcn_bw_v_max0p91; 1364 BREAK_TO_DEBUGGER(); 1365 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) { 1366 vdd_level = dcn_bw_v_max0p9; 1367 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) { 1368 vdd_level = dcn_bw_v_nom0p8; 1369 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) { 1370 vdd_level = dcn_bw_v_mid0p72; 1371 } else 1372 vdd_level = dcn_bw_v_min0p65; 1373 break; 1374 1375 default: 1376 break; 1377 } 1378 return vdd_level; 1379 } 1380 1381 unsigned int dcn_find_dcfclk_suits_all( 1382 const struct dc *dc, 1383 struct dc_clocks *clocks) 1384 { 1385 unsigned vdd_level, vdd_level_temp; 1386 unsigned dcf_clk; 1387 1388 /*find a common supported voltage level*/ 1389 vdd_level = dcn_find_normalized_clock_vdd_Level( 1390 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz); 1391 vdd_level_temp = dcn_find_normalized_clock_vdd_Level( 1392 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz); 1393 1394 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp); 1395 vdd_level_temp = dcn_find_normalized_clock_vdd_Level( 1396 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz); 1397 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp); 1398 1399 vdd_level_temp = dcn_find_normalized_clock_vdd_Level( 1400 dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz); 1401 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp); 1402 vdd_level_temp = dcn_find_normalized_clock_vdd_Level( 1403 dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz); 1404 1405 /*find that level conresponding dcfclk*/ 1406 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp); 1407 if (vdd_level == dcn_bw_v_max0p91) { 1408 BREAK_TO_DEBUGGER(); 1409 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000; 1410 } else if (vdd_level == dcn_bw_v_max0p9) 1411 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000; 1412 else if (vdd_level == dcn_bw_v_nom0p8) 1413 dcf_clk = dc->dcn_soc->dcfclkv_nom0p8*1000; 1414 else if (vdd_level == dcn_bw_v_mid0p72) 1415 dcf_clk = dc->dcn_soc->dcfclkv_mid0p72*1000; 1416 else 1417 dcf_clk = dc->dcn_soc->dcfclkv_min0p65*1000; 1418 1419 DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk); 1420 return dcf_clk; 1421 } 1422 1423 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) 1424 { 1425 int i; 1426 1427 if (clks->num_levels == 0) 1428 return false; 1429 1430 for (i = 0; i < clks->num_levels; i++) 1431 /* Ensure that the result is sane */ 1432 if (clks->data[i].clocks_in_khz == 0) 1433 return false; 1434 1435 return true; 1436 } 1437 1438 void dcn_bw_update_from_pplib(struct dc *dc) 1439 { 1440 struct dc_context *ctx = dc->ctx; 1441 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; 1442 bool res; 1443 unsigned vmin0p65_idx, vmid0p72_idx, vnom0p8_idx, vmax0p9_idx; 1444 1445 /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */ 1446 res = dm_pp_get_clock_levels_by_type_with_voltage( 1447 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); 1448 1449 DC_FP_START(); 1450 1451 if (res) 1452 res = verify_clock_values(&fclks); 1453 1454 if (res) { 1455 ASSERT(fclks.num_levels); 1456 1457 vmin0p65_idx = 0; 1458 vmid0p72_idx = fclks.num_levels - 1459 (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1)); 1460 vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1); 1461 vmax0p9_idx = fclks.num_levels - 1; 1462 1463 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 1464 32 * (fclks.data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0; 1465 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 1466 dc->dcn_soc->number_of_channels * 1467 (fclks.data[vmid0p72_idx].clocks_in_khz / 1000.0) 1468 * ddr4_dram_factor_single_Channel / 1000.0; 1469 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 1470 dc->dcn_soc->number_of_channels * 1471 (fclks.data[vnom0p8_idx].clocks_in_khz / 1000.0) 1472 * ddr4_dram_factor_single_Channel / 1000.0; 1473 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 1474 dc->dcn_soc->number_of_channels * 1475 (fclks.data[vmax0p9_idx].clocks_in_khz / 1000.0) 1476 * ddr4_dram_factor_single_Channel / 1000.0; 1477 } else 1478 BREAK_TO_DEBUGGER(); 1479 1480 DC_FP_END(); 1481 1482 res = dm_pp_get_clock_levels_by_type_with_voltage( 1483 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks); 1484 1485 DC_FP_START(); 1486 1487 if (res) 1488 res = verify_clock_values(&dcfclks); 1489 1490 if (res && dcfclks.num_levels >= 3) { 1491 dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0; 1492 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0; 1493 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0; 1494 dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0; 1495 } else 1496 BREAK_TO_DEBUGGER(); 1497 1498 DC_FP_END(); 1499 } 1500 1501 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) 1502 { 1503 struct pp_smu_funcs_rv *pp = NULL; 1504 struct pp_smu_wm_range_sets ranges = {0}; 1505 volatile int min_fclk_khz, min_dcfclk_khz, socclk_khz; 1506 const int overdrive = 5000000; /* 5 GHz to cover Overdrive */ 1507 1508 if (dc->res_pool->pp_smu) 1509 pp = &dc->res_pool->pp_smu->rv_funcs; 1510 if (!pp || !pp->set_wm_ranges) 1511 return; 1512 1513 DC_FP_START(); 1514 min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32; 1515 min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000; 1516 socclk_khz = dc->dcn_soc->socclk * 1000; 1517 DC_FP_END(); 1518 1519 /* Now notify PPLib/SMU about which Watermarks sets they should select 1520 * depending on DPM state they are in. And update BW MGR GFX Engine and 1521 * Memory clock member variables for Watermarks calculations for each 1522 * Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254. 1523 */ 1524 /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont 1525 * care what the value is, hence min to overdrive level 1526 */ 1527 ranges.num_reader_wm_sets = WM_SET_COUNT; 1528 ranges.num_writer_wm_sets = WM_SET_COUNT; 1529 ranges.reader_wm_sets[0].wm_inst = WM_A; 1530 ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000; 1531 ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000; 1532 ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000; 1533 ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000; 1534 ranges.writer_wm_sets[0].wm_inst = WM_A; 1535 ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000; 1536 ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000; 1537 ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000; 1538 ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000; 1539 1540 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) { 1541 ranges.reader_wm_sets[0].wm_inst = WM_A; 1542 ranges.reader_wm_sets[0].min_drain_clk_mhz = 300; 1543 ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000; 1544 ranges.reader_wm_sets[0].min_fill_clk_mhz = 800; 1545 ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000; 1546 ranges.writer_wm_sets[0].wm_inst = WM_A; 1547 ranges.writer_wm_sets[0].min_fill_clk_mhz = 200; 1548 ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000; 1549 ranges.writer_wm_sets[0].min_drain_clk_mhz = 800; 1550 ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000; 1551 } 1552 1553 ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0]; 1554 ranges.reader_wm_sets[1].wm_inst = WM_B; 1555 1556 ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0]; 1557 ranges.reader_wm_sets[2].wm_inst = WM_C; 1558 1559 ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0]; 1560 ranges.reader_wm_sets[3].wm_inst = WM_D; 1561 1562 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1563 pp->set_wm_ranges(&pp->pp_smu, &ranges); 1564 } 1565 1566 void dcn_bw_sync_calcs_and_dml(struct dc *dc) 1567 { 1568 DC_FP_START(); 1569 DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n" 1570 "sr_enter_plus_exit_time: %f ns\n" 1571 "urgent_latency: %f ns\n" 1572 "write_back_latency: %f ns\n" 1573 "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n" 1574 "max_request_size: %d bytes\n" 1575 "dcfclkv_max0p9: %f kHz\n" 1576 "dcfclkv_nom0p8: %f kHz\n" 1577 "dcfclkv_mid0p72: %f kHz\n" 1578 "dcfclkv_min0p65: %f kHz\n" 1579 "max_dispclk_vmax0p9: %f kHz\n" 1580 "max_dispclk_vnom0p8: %f kHz\n" 1581 "max_dispclk_vmid0p72: %f kHz\n" 1582 "max_dispclk_vmin0p65: %f kHz\n" 1583 "max_dppclk_vmax0p9: %f kHz\n" 1584 "max_dppclk_vnom0p8: %f kHz\n" 1585 "max_dppclk_vmid0p72: %f kHz\n" 1586 "max_dppclk_vmin0p65: %f kHz\n" 1587 "socclk: %f kHz\n" 1588 "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n" 1589 "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n" 1590 "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n" 1591 "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n" 1592 "phyclkv_max0p9: %f kHz\n" 1593 "phyclkv_nom0p8: %f kHz\n" 1594 "phyclkv_mid0p72: %f kHz\n" 1595 "phyclkv_min0p65: %f kHz\n" 1596 "downspreading: %f %%\n" 1597 "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n" 1598 "urgent_out_of_order_return_per_channel: %d Bytes\n" 1599 "number_of_channels: %d\n" 1600 "vmm_page_size: %d Bytes\n" 1601 "dram_clock_change_latency: %f ns\n" 1602 "return_bus_width: %d Bytes\n", 1603 dc->dcn_soc->sr_exit_time * 1000, 1604 dc->dcn_soc->sr_enter_plus_exit_time * 1000, 1605 dc->dcn_soc->urgent_latency * 1000, 1606 dc->dcn_soc->write_back_latency * 1000, 1607 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency, 1608 dc->dcn_soc->max_request_size, 1609 dc->dcn_soc->dcfclkv_max0p9 * 1000, 1610 dc->dcn_soc->dcfclkv_nom0p8 * 1000, 1611 dc->dcn_soc->dcfclkv_mid0p72 * 1000, 1612 dc->dcn_soc->dcfclkv_min0p65 * 1000, 1613 dc->dcn_soc->max_dispclk_vmax0p9 * 1000, 1614 dc->dcn_soc->max_dispclk_vnom0p8 * 1000, 1615 dc->dcn_soc->max_dispclk_vmid0p72 * 1000, 1616 dc->dcn_soc->max_dispclk_vmin0p65 * 1000, 1617 dc->dcn_soc->max_dppclk_vmax0p9 * 1000, 1618 dc->dcn_soc->max_dppclk_vnom0p8 * 1000, 1619 dc->dcn_soc->max_dppclk_vmid0p72 * 1000, 1620 dc->dcn_soc->max_dppclk_vmin0p65 * 1000, 1621 dc->dcn_soc->socclk * 1000, 1622 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000, 1623 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000, 1624 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000, 1625 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000, 1626 dc->dcn_soc->phyclkv_max0p9 * 1000, 1627 dc->dcn_soc->phyclkv_nom0p8 * 1000, 1628 dc->dcn_soc->phyclkv_mid0p72 * 1000, 1629 dc->dcn_soc->phyclkv_min0p65 * 1000, 1630 dc->dcn_soc->downspreading * 100, 1631 dc->dcn_soc->round_trip_ping_latency_cycles, 1632 dc->dcn_soc->urgent_out_of_order_return_per_channel, 1633 dc->dcn_soc->number_of_channels, 1634 dc->dcn_soc->vmm_page_size, 1635 dc->dcn_soc->dram_clock_change_latency * 1000, 1636 dc->dcn_soc->return_bus_width); 1637 DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n" 1638 "det_buffer_size_in_kbyte: %f\n" 1639 "dpp_output_buffer_pixels: %f\n" 1640 "opp_output_buffer_lines: %f\n" 1641 "pixel_chunk_size_in_kbyte: %f\n" 1642 "pte_enable: %d\n" 1643 "pte_chunk_size: %d kbytes\n" 1644 "meta_chunk_size: %d kbytes\n" 1645 "writeback_chunk_size: %d kbytes\n" 1646 "odm_capability: %d\n" 1647 "dsc_capability: %d\n" 1648 "line_buffer_size: %d bits\n" 1649 "max_line_buffer_lines: %d\n" 1650 "is_line_buffer_bpp_fixed: %d\n" 1651 "line_buffer_fixed_bpp: %d\n" 1652 "writeback_luma_buffer_size: %d kbytes\n" 1653 "writeback_chroma_buffer_size: %d kbytes\n" 1654 "max_num_dpp: %d\n" 1655 "max_num_writeback: %d\n" 1656 "max_dchub_topscl_throughput: %d pixels/dppclk\n" 1657 "max_pscl_tolb_throughput: %d pixels/dppclk\n" 1658 "max_lb_tovscl_throughput: %d pixels/dppclk\n" 1659 "max_vscl_tohscl_throughput: %d pixels/dppclk\n" 1660 "max_hscl_ratio: %f\n" 1661 "max_vscl_ratio: %f\n" 1662 "max_hscl_taps: %d\n" 1663 "max_vscl_taps: %d\n" 1664 "pte_buffer_size_in_requests: %d\n" 1665 "dispclk_ramping_margin: %f %%\n" 1666 "under_scan_factor: %f %%\n" 1667 "max_inter_dcn_tile_repeaters: %d\n" 1668 "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n" 1669 "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n" 1670 "dcfclk_cstate_latency: %d\n", 1671 dc->dcn_ip->rob_buffer_size_in_kbyte, 1672 dc->dcn_ip->det_buffer_size_in_kbyte, 1673 dc->dcn_ip->dpp_output_buffer_pixels, 1674 dc->dcn_ip->opp_output_buffer_lines, 1675 dc->dcn_ip->pixel_chunk_size_in_kbyte, 1676 dc->dcn_ip->pte_enable, 1677 dc->dcn_ip->pte_chunk_size, 1678 dc->dcn_ip->meta_chunk_size, 1679 dc->dcn_ip->writeback_chunk_size, 1680 dc->dcn_ip->odm_capability, 1681 dc->dcn_ip->dsc_capability, 1682 dc->dcn_ip->line_buffer_size, 1683 dc->dcn_ip->max_line_buffer_lines, 1684 dc->dcn_ip->is_line_buffer_bpp_fixed, 1685 dc->dcn_ip->line_buffer_fixed_bpp, 1686 dc->dcn_ip->writeback_luma_buffer_size, 1687 dc->dcn_ip->writeback_chroma_buffer_size, 1688 dc->dcn_ip->max_num_dpp, 1689 dc->dcn_ip->max_num_writeback, 1690 dc->dcn_ip->max_dchub_topscl_throughput, 1691 dc->dcn_ip->max_pscl_tolb_throughput, 1692 dc->dcn_ip->max_lb_tovscl_throughput, 1693 dc->dcn_ip->max_vscl_tohscl_throughput, 1694 dc->dcn_ip->max_hscl_ratio, 1695 dc->dcn_ip->max_vscl_ratio, 1696 dc->dcn_ip->max_hscl_taps, 1697 dc->dcn_ip->max_vscl_taps, 1698 dc->dcn_ip->pte_buffer_size_in_requests, 1699 dc->dcn_ip->dispclk_ramping_margin, 1700 dc->dcn_ip->under_scan_factor * 100, 1701 dc->dcn_ip->max_inter_dcn_tile_repeaters, 1702 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one, 1703 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed, 1704 dc->dcn_ip->dcfclk_cstate_latency); 1705 1706 dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; 1707 dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time; 1708 dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency; 1709 dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency; 1710 dc->dml.soc.ideal_dram_bw_after_urgent_percent = 1711 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency; 1712 dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size; 1713 dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading; 1714 dc->dml.soc.round_trip_ping_latency_dcfclk_cycles = 1715 dc->dcn_soc->round_trip_ping_latency_cycles; 1716 dc->dml.soc.urgent_out_of_order_return_per_channel_bytes = 1717 dc->dcn_soc->urgent_out_of_order_return_per_channel; 1718 dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels; 1719 dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size; 1720 dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency; 1721 dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width; 1722 1723 dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte; 1724 dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte; 1725 dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels; 1726 dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines; 1727 dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte; 1728 dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes; 1729 dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size; 1730 dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size; 1731 dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size; 1732 dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size; 1733 dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines; 1734 dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes; 1735 dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp; 1736 dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size; 1737 dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size; 1738 dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp; 1739 dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback; 1740 dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput; 1741 dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput; 1742 dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput; 1743 dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput; 1744 dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio; 1745 dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio; 1746 dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps; 1747 dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps; 1748 /*pte_buffer_size_in_requests missing in dml*/ 1749 dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin; 1750 dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor; 1751 dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters; 1752 dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 1753 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes; 1754 dc->dml.ip.bug_forcing_LC_req_same_size_fixed = 1755 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes; 1756 dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency; 1757 DC_FP_END(); 1758 } 1759
Indexes created Mon Sep 22 05:09:51 GMT 2025