HomeSort by: relevance | last modified time | path
    Searched refs:hasOrderedMemoryRef (Results 1 - 20 of 20) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
RDFDeadCode.cpp 61 if (MI->hasOrderedMemoryRef() || MI->hasUnmodeledSideEffects() ||
HexagonStoreWidening.cpp 275 if (MI->hasOrderedMemoryRef() || instrAliased(Group, MI))
HexagonExpandCondsets.cpp 833 bool Ordered = TheI.hasOrderedMemoryRef();
843 if (Ordered && MI->hasOrderedMemoryRef())
HexagonVLIWPacketizer.cpp 1516 bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
HexagonInstrInfo.cpp 1901 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIOptimizeExecMaskingPreRA.cpp 373 I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
SILoadStoreOptimizer.cpp 975 if (MBBI->hasOrderedMemoryRef())
2004 if (MI.hasOrderedMemoryRef()) {
SIInstrInfo.cpp 2980 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiInstrInfo.cpp 94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64LoadStoreOptimizer.cpp 1298 if (MI.hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
1302 assert(!FirstMI.hasOrderedMemoryRef() &&
2043 if (MI.hasOrderedMemoryRef())
AArch64InstrInfo.cpp 1065 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
2449 if (MI.hasOrderedMemoryRef())
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVInstrInfo.cpp 927 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstr.h 1626 bool hasOrderedMemoryRef() const;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsDelaySlotFiller.cpp 469 if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRegStackify.cpp 181 } else if (MI.hasOrderedMemoryRef()) {
201 // moved, however hasOrderedMemoryRef() interprets this plus their lack
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineInstr.cpp 1239 (mayLoad() && hasOrderedMemoryRef())) {
1372 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1376 bool MachineInstr::hasOrderedMemoryRef() const {
MachineSink.cpp 1187 if (I.isCall() || I.hasOrderedMemoryRef()) {
ScheduleDAGInstrs.cpp 545 (MI->hasOrderedMemoryRef() && !MI->isDereferenceableInvariantLoad(AA));
MachinePipeliner.cpp 712 (MI.hasOrderedMemoryRef() &&
2299 SI->hasOrderedMemoryRef() || DI->hasOrderedMemoryRef())
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 2751 if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3)
5476 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())

Completed in 71 milliseconds