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  /src/sys/dev/videomode/
modelines2c.awk 81 htotal = $7;
111 hrefresh= (dotclock * 1000000) / htotal;
121 hsyncstart, hsyncend, htotal,
130 hsyncstart/2, hsyncend/2, htotal/2,
videomode.h 38 int htotal; member in struct:videomode
pickmode.c 80 mref = this->dot_clock * 1000 / (this->htotal * this->vtotal);
133 (*preferred)->htotal), (*preferred)->vtotal);
159 mtemp->htotal), mtemp->vtotal);
173 modes[i].htotal), modes[i].vtotal));
vesagtf.c 620 vmp->htotal = total_pixels;
666 hf = 1000.0 * vmp->dot_clock / vmp->htotal;
678 vmp->hdisplay, vmp->hsync_start, vmp->hsync_end, vmp->htotal,
edid.c 275 edid->edid_modes[i].htotal), edid->edid_modes[i].vtotal));
280 edid->edid_modes[i].htotal,
295 edid->edid_preferred_mode->htotal),
318 mode->htotal), mode->vtotal);
324 edid->edid_modes[i].htotal), edid->edid_modes[i].vtotal)) {
405 vmp->htotal = hactive + hblank;
  /src/sys/dev/ic/
mc6845reg.h 30 u_int8_t htotal, hdisple, hblanks, hblanke; member in struct:reg_mc6845
  /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvif/
cl0046.h 28 __u16 htotal; member in struct:nv04_disp_scanoutpos_v0
cl5070.h 27 __u16 htotal; member in struct:nv50_disp_scanoutpos_v0
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/
nouveau_nvkm_engine_disp_head.c 65 args->v0.htotal = head->arm.htotal;
69 /* We don't support reading htotal/vtotal on pre-NV50 VGA,
73 if (!args->v0.vtotal || !args->v0.htotal)
nouveau_nvkm_engine_disp_headnv04.c 63 state->htotal = nvkm_rd32(device, 0x680824 + hoff) & 0x0000ffff;
64 state->hblanke = state->htotal - 1;
head.h 16 u16 htotal; member in struct:nvkm_head::nvkm_head_state
nouveau_nvkm_engine_disp_headgf119.c 63 state->htotal = (data & 0x0000ffff);
nouveau_nvkm_engine_disp_headgv100.c 62 state->htotal = (data & 0x0000ffff);
  /src/usr.sbin/grfconfig/
grfconfig.c 177 gv->htotal = atoi(cps[8]);
201 (gv->htotal == 0) ||
249 if ((gv->htotal < (gv->disp_width / 4))) {
253 gv->htotal *= 8;
329 gv->pixel_clock / (gv->htotal * 1000),
330 (gv->pixel_clock / (gv->htotal * 100))
332 gv->pixel_clock / (gv->htotal * gv->vtotal));
379 gv->htotal,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_rq_dlg_calc_20.c 793 unsigned int htotal = dst->htotal; local in function:dml20_rq_dlg_get_dlg_params
923 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
934 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
984 line_time_in_us = (htotal / pclk_freq_in_mhz);
1031 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1038 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1069 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal);
1108 if (htotal <= 75)
    [all...]
amdgpu_display_rq_dlg_calc_20v2.c 793 unsigned int htotal = dst->htotal; local in function:dml20v2_rq_dlg_get_dlg_params
923 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
934 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
985 line_time_in_us = (htotal / pclk_freq_in_mhz);
1032 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1039 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1070 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal);
1109 if (htotal <= 75)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_rq_dlg_calc_21.c 839 unsigned int htotal = dst->htotal; local in function:dml_rq_dlg_get_dlg_params
969 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
980 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
1036 line_time_in_us = (htotal / pclk_freq_in_mhz);
1071 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1078 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1112 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal);
1158 if (htotal <= 75)
    [all...]
  /src/sys/external/bsd/drm2/dist/include/drm/
drm_modes.h 140 .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
157 .htotal = (hd), .vdisplay = (vd), .vsync_start = (vd), \
180 * @htotal: horizontal total size
287 int htotal; member in struct:drm_display_mode
445 (m)->hdisplay, (m)->hsync_start, (m)->hsync_end, (m)->htotal, \
  /src/sys/external/bsd/drm2/dist/drm/
drm_modes.c 287 drm_mode->htotal = drm_mode->hdisplay + hblank;
290 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100;
321 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK;
330 tmp = drm_mode->htotal; /* perform intermediate calcs in u64 */
523 drm_mode->htotal = total_pixels;
604 dmode->htotal = dmode->hsync_end + vm->hback_porch;
645 vm->hback_porch = dmode->htotal - dmode->hsync_end;
775 if (mode->htotal <= 0)
778 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */
800 else if (mode->htotal > 0 && mode->vtotal > 0)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_tv.c 320 u16 hblank_start, hblank_end, htotal; member in struct:tv_mode
394 .hblank_start = 836, .htotal = 857,
436 .hblank_start = 836, .htotal = 857,
479 .hblank_start = 836, .htotal = 857,
522 .hblank_start = 836, .htotal = 857,
565 .hblank_start = 844, .htotal = 863,
610 .hblank_start = 844, .htotal = 863,
652 .hblank_start = 842, .htotal = 857,
676 .hblank_start = 859, .htotal = 863,
700 .hblank_start = 1580, .htotal = 1649
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/
nouveau_nvkm_subdev_devinit_nv04.c 420 u32 htotal = nvkm_rdvgac(device, 0, 0x06); local in function:nv04_devinit_preinit
421 htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x01) << 8;
422 htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x20) << 4;
423 htotal |= (nvkm_rdvgac(device, 0, 0x25) & 0x01) << 10;
424 htotal |= (nvkm_rdvgac(device, 0, 0x41) & 0x01) << 11;
425 if (!htotal) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calc_auto.c 181 v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k] * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) * v->v_ratio[k] +dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0 * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]);
199 v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
202 v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
247 if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0 > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) {
250 else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) >dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) {
564 v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]);
567 v->urgent_latency_support_us_per_state[i][j][k] =dcn_bw_min2(v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]), v->effective_detlb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_detlb_lines_chroma * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]));
790 v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
807 v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v (…)
    [all...]
  /src/sys/arch/arm/iomd/
vidc20config.c 352 modes[i].htotal * 2 / modes[i].vtotal + 1) / 2;
485 vidcvideo_write(VIDC_HBSR, (vm->htotal - vm->hsync_start - 12) & ~1);
486 vidcvideo_write(VIDC_HDSR, (vm->htotal - vm->hsync_start - 18) & ~1);
488 (vm->htotal - vm->hsync_start + vm->hdisplay - 18) & ~1);
490 (vm->htotal - vm->hsync_start + vm->hdisplay - 12) & ~1);
491 vidcvideo_write(VIDC_HCR, (vm->htotal - 8) & ~3);
652 int frontporch = vidc_currentmode.timings.htotal -
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
amdgpu_dml1_display_rq_dlg_calc.c 997 unsigned int htotal = e2e_pipe_param.pipe.dest.htotal; local in function:dml1_rq_dlg_get_dlg_params
1142 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
1159 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
1211 line_time_in_us = (htotal / pclk_freq_in_mhz);
1277 if (dst_x_after_scaler >= htotal) {
1278 dst_x_after_scaler = dst_x_after_scaler - htotal;
1282 DTRACE("DLG: %s: htotal = %d", __func__, htotal);
1300 line_o = (double) dst_y_after_scaler + dst_x_after_scaler / (double) htotal;
    [all...]
  /src/sys/arch/amiga/dev/
grfioctl.h 92 u_short htotal; /* your monitor ! */ member in struct:grfvideo_mode

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