| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| hubp.h | 1 /* $NetBSD: hubp.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
55 struct hubp { struct
90 struct hubp *hubp,
97 struct hubp *hubp,
101 void (*dcc_control)(struct hubp *hubp, bool enable,
105 struct hubp *hubp,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_hubp.h | 33 #define TO_DCN20_HUBP(hubp)\
34 container_of(hubp, struct dcn20_hubp, base)
211 struct hubp base;
227 struct hubp *hubp,
231 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
235 struct hubp *hubp,
238 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp
[all...] |
| amdgpu_dcn20_hubp.c | 50 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
53 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
85 struct hubp *hubp,
89 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
91 /* DLG - Per hubp */
148 /* TTU - per hubp */
175 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
[all...] |
| amdgpu_dcn20_hwseq.c | 45 #include "hubp.h"
181 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
182 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
183 pipe_ctx->plane_res.hubp, flip_immediate);
268 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
269 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
270 pipe_ctx->plane_res.hubp,
562 struct hubp *hubp = pipe_ctx->plane_res.hubp local in function:dcn20_plane_atomic_disable
1316 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn20_update_dchubp_dpp
1649 struct hubp *hubp = pipe->plane_res.hubp; local in function:dcn20_program_front_end_for_ctx
1816 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn20_dmdata_status_done
1856 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn20_set_dmdata_attributes
2141 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn20_update_mpcc
2266 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn20_program_dmdata_engine
2353 struct hubp *hubp = dc->res_pool->hubps[i]; local in function:dcn20_fpga_init_hw
[all...] |
| dcn20_resource.h | 106 struct hubp *dcn20_hubp_create(
|
| amdgpu_dcn20_resource.c | 1425 struct hubp *dcn20_hubp_create(
1738 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1813 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
3002 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hubp.c | 46 void hubp1_set_blank(struct hubp *hubp, bool blank)
48 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
59 /* init sequence workaround: in case HUBP is
63 * it means HUBP is gated
70 hubp->mpcc_id = 0xf;
71 hubp->opp_id = OPP_ID_INVALID;
75 static void hubp1_disconnect(struct hubp *hubp)
77 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
[all...] |
| dcn10_hubp.h | 30 #include "hubp.h"
32 #define TO_DCN10_HUBP(hubp)\
33 container_of(hubp, struct dcn10_hubp, base)
37 SRI(DCHUBP_CNTL, HUBP, id),\
38 SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
39 SRI(HUBPREQ_DEBUG, HUBP, id),\
40 SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
41 SRI(DCSURF_TILING_CONFIG, HUBP, id),\
44 SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
46 SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id),
[all...] |
| amdgpu_dcn10_hw_sequencer.c | 166 "HUBP: format addr_hi width height rot mir sw_mode dcc_en blank_en clock_en ttu_dis underflow min_ttu_vblank qos_low_wm qos_high_wm\n");
168 struct hubp *hubp = pool->hubps[i]; local in function:dcn10_log_hubp_states
169 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
171 hubp->funcs->hubp_read_state(hubp);
175 hubp->inst,
196 DTN_INFO("HUBP: drq_exp_m prq_exp_m mrq_exp_m crq_exp_m plane1_ba L:chunk_s min_chu_s meta_ch_s"
217 DTN_INFO("HUBP: rc_hbe dlg_vbe min_d_y_n rc_per_ht rc_x_a_s "
253 DTN_INFO("HUBP: qos_ll_wm qos_lh_wm mn_ttu_vb qos_l_flp rc_rd_p_l rc_rd_l rc_rd_p_c
468 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn10_did_underflow_occur
662 struct hubp *hubp = dc->res_pool->hubps[0]; local in function:undo_DEGVIDCN10_253_wa
682 struct hubp *hubp = dc->res_pool->hubps[0]; local in function:apply_DEGVIDCN10_253_wa
930 struct hubp *hubp ; local in function:dcn10_hw_wa_force_recovery
1033 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn10_plane_atomic_disconnect
1086 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn10_plane_atomic_disable
1185 struct hubp *hubp = dc->res_pool->hubps[i]; local in function:dcn10_init_pipes
2139 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn10_update_mpcc
2239 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn10_update_dchubp_dpp
2864 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); local in function:dcn10_wait_for_mpcc_disconnect
2949 struct hubp *hubp = pipe_ctx->plane_res.hubp; local in function:dcn10_set_cursor_position
[all...] |
| amdgpu_dcn10_hw_sequencer_debug.c | 139 struct hubp *hubp = pool->hubps[i]; local in function:dcn10_get_hubp_states
140 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
142 hubp->funcs->hubp_read_state(hubp);
149 hubp->inst,
168 hubp->inst,
515 struct hubp *hubp = pool->hubps[i]; local in function:dcn10_clear_hubp_underflow
516 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state)
[all...] |
| dcn10_hw_sequencer.h | 178 struct hubp *hubp);
|
| amdgpu_dcn10_resource.c | 1014 static struct hubp *dcn10_hubp_create(
1154 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| dcn21_hubp.h | 34 #define TO_DCN21_HUBP(hubp)\
35 container_of(hubp, struct dcn21_hubp, base)
108 struct hubp base;
125 struct hubp *hubp,
129 struct hubp *hubp,
134 struct hubp *hubp,
|
| amdgpu_dcn21_hubp.c | 83 struct hubp *hubp,
86 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
118 struct hubp *hubp,
122 hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
124 apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);
128 struct hubp *hubp,
131 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
[all...] |
| amdgpu_dcn21_resource.c | 1212 static struct hubp *dcn21_hubp_create(
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| hw_sequencer_private.h | 62 struct hubp;
110 struct hubp *hubp);
|
| core_types.h | 37 #include "hubp.h"
162 struct hubp *hubps[MAX_PIPES];
249 struct hubp *hubp; member in struct:plane_resource
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_stream.c | 349 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||
606 /* Stream not found, by default we'll assume HUBP fetched dm data */
618 struct hubp *hubp; local in function:dc_stream_set_dynamic_metadata
638 hubp = pipe_ctx->plane_res.hubp;
639 if (hubp == NULL)
646 if (hubp->funcs->dmdata_set_attributes != NULL &&
648 hubp->funcs->dmdata_set_attributes(hubp, attr)
[all...] |
| amdgpu_dc_resource.c | 1245 split_pipe->plane_res.hubp = pool->hubps[i];
1648 pipe_ctx->plane_res.hubp = pool->hubps[i];
1919 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
|
| amdgpu_dc.c | 63 #include "hubp.h"
2266 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2267 cur_pipe.plane_res.hubp, dc->ctx,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dmub_psr.c | 146 if (pipe_ctx->plane_res.hubp)
147 copy_settings_data->hubp_inst = pipe_ctx->plane_res.hubp->inst;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 526 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
|
