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    Searched refs:hw_internal_rev (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/
amdgpu_clk_mgr.c 117 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
118 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
122 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
123 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
124 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
128 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
134 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
142 if (ASICREV_IS_DALI(asic_id.hw_internal_rev) ||
143 ASICREV_IS_POLLOCK(asic_id.hw_internal_rev)) {
149 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/
amdgpu_dce112_clk_mgr.c 109 if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))
185 if (!ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_resource.c 72 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
73 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
74 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
84 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
85 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
89 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
90 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
91 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
94 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
98 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
    [all...]
amdgpu_dc_stream.c 248 ASICREV_IS_RAVEN(stream->ctx->asic_id.hw_internal_rev)) {
amdgpu_dc_link.c 2575 if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
amdgpu_dce110_clk_mgr.c 203 if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 1231 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3223 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3297 uint32_t hw_internal_rev)
3299 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3306 uint32_t hw_internal_rev)
3309 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3316 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3329 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3331 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3336 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_types.h 84 uint32_t hw_internal_rev; member in struct:hw_asic_id
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 711 unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev)
714 if (ASICREV_IS_POLLOCK(hw_internal_rev) || ASICREV_IS_DALI(hw_internal_rev))
1285 if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev))
amdgpu_dce_calcs.c 59 if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev))
64 if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
66 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
68 if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
70 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_resource.c 562 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
1316 if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_resource.c 1186 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1187 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_resource.c 1442 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1459 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_clk_mgr.c 325 if (!ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_resource.c 1042 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c 904 init_data.asic_id.hw_internal_rev = adev->external_rev_id;

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