| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_hw_sequencer.c | 83 dc->hwss.pipe_control_lock = dce_pipe_control_lock;
84 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
85 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_vm_helper.c | 46 /* Call HWSS to setup HUBBUB for address config */
47 if (dc->hwss.init_sys_ctx) {
48 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config);
62 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid);
|
| amdgpu_dc_stream.c | 250 vupdate_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
308 dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
311 dc->hwss.set_cursor_attribute(pipe_ctx);
312 if (dc->hwss.set_cursor_sdr_white_level)
313 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
317 dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
359 dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
362 dc->hwss.set_cursor_position(pipe_ctx);
366 dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
414 if (dc->hwss.enable_writeback)
[all...] |
| amdgpu_dc.c | 295 dc->hwss.set_drr(&pipe,
323 dc->hwss.get_position(&pipe, 1, &position);
487 dc->hwss.program_gamut_remap(pipes);
506 dc->hwss.program_output_csc(dc,
540 dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
794 if (dc->hwss.apply_ctx_for_surface)
795 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
797 if (dc->hwss.program_front_end_for_ctx)
798 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
822 dc->hwss.update_pending_status(pipe)
[all...] |
| amdgpu_dc_link_hwss.c | 223 link->dc->hwss.edp_power_control(link, false);
336 link->dc->hwss.disable_stream(&pipes[i]);
355 link->dc->hwss.enable_stream(&pipes[i]);
357 link->dc->hwss.unblank_stream(&pipes[i],
|
| amdgpu_dc_link.c | 229 link->dc->hwss.edp_power_control(link, true);
230 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1514 link->dc->hwss.edp_power_control(link, true);
1515 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
2998 dc->hwss.update_info_frame(pipe_ctx);
3041 dc->hwss.enable_audio_stream(pipe_ctx);
3054 dc->hwss.enable_stream(pipe_ctx);
3066 dc->hwss.unblank_stream(pipe_ctx,
3096 dc->hwss.blank_stream(pipe_ctx);
3125 dc->hwss.disable_stream(pipe_ctx)
[all...] |
| amdgpu_dc_surface.c | 179 dc->hwss.update_pending_status(pipe_ctx);
|
| amdgpu_dc_link_dp.c | 984 /* 1. call HWSS to set lane settings*/
1397 /* call HWSS to set lane settings*/
1408 /* call HWSS to set lane settings*/
3825 link->dc->hwss.unblank_stream(
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/ |
| amdgpu_clk_mgr.c | 75 if (dc->hwss.exit_optimized_pwr_state)
76 dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
92 if (dc->hwss.optimize_pwr_state)
93 dc->hwss.optimize_pwr_state(dc, dc->current_state);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_hw_sequencer.c | 144 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
145 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_init.c | 131 dc->hwss = dcn20_funcs;
135 dc->hwss.init_hw = dcn20_fpga_init_hw;
|
| amdgpu_dcn20_hwseq.c | 565 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
573 dc->hwss.set_flip_control_gsl(pipe_ctx, false);
1411 dc->hwss.set_cursor_position(pipe_ctx);
1412 dc->hwss.set_cursor_attribute(pipe_ctx);
1414 if (dc->hwss.set_cursor_sdr_white_level)
1415 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1424 dc->hwss.program_gamut_remap(pipe_ctx);
1427 dc->hwss.program_output_csc(dc,
1581 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
1583 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], true)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_init.c | 140 dc->hwss = dcn21_funcs;
144 dc->hwss.init_hw = dcn20_fpga_init_hw;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_init.c | 114 dc->hwss = dcn10_funcs;
|
| amdgpu_dcn10_hw_sequencer.c | 767 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
886 dc->hwss.disable_audio_stream(pipe_ctx);
1090 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
1230 dc->hwss.disable_plane(dc, pipe_ctx);
2317 dc->hwss.set_cursor_position(pipe_ctx);
2318 dc->hwss.set_cursor_attribute(pipe_ctx);
2320 if (dc->hwss.set_cursor_sdr_white_level)
2321 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
2326 dc->hwss.program_gamut_remap(pipe_ctx);
2328 dc->hwss.program_output_csc(dc
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 274 dc->hwss.update_dchub = dce120_update_dchub;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_debugfs.c | 1036 if (!dc->hwss.log_hw_state)
1039 dc->hwss.log_hw_state(dc, &log_ctx);
1074 if (dc->hwss.log_hw_state)
1075 dc->hwss.log_hw_state(dc, NULL);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 676 dc->hwss.update_info_frame(pipe_ctx);
1041 dc->hwss.disable_audio_stream(pipe_ctx);
1515 dc->hwss.disable_plane(dc,
1613 dc->hwss.edp_power_control(edp_link_with_sink, false);
1933 dc->hwss.disable_plane(dc, pipe_ctx_old);
2521 /* Moved programming gamma from dc to hwss */
2589 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2609 dc->hwss.update_plane_addr(dc, pipe_ctx);
2622 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2775 dc->hwss = dce110_funcs
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc.h | 518 struct hw_sequencer_funcs hwss; member in struct:dc
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_hwseq.h | 820 void dce_enable_fe_clock(struct dce_hwseq *hwss,
|
