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    Searched refs:i915_mmio_reg_offset (Results 1 - 25 of 32) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/i915/
intel_uncore.h 287 return bus_space_read_1(uncore->regs_bst, uncore->regs_bsh, i915_mmio_reg_offset(reg));
291 return bus_space_read_2(uncore->regs_bst, uncore->regs_bsh, i915_mmio_reg_offset(reg));
295 return bus_space_read_4(uncore->regs_bst, uncore->regs_bsh, i915_mmio_reg_offset(reg));
300 return bus_space_read_8(uncore->regs_bst, uncore->regs_bsh, i915_mmio_reg_offset(reg));
304 i915_mmio_reg_offset(reg));
306 i915_mmio_reg_offset(reg) + 4);
312 bus_space_write_1(uncore->regs_bst, uncore->regs_bsh, i915_mmio_reg_offset(reg), val);
316 bus_space_write_2(uncore->regs_bst, uncore->regs_bsh, i915_mmio_reg_offset(reg), val);
320 bus_space_write_4(uncore->regs_bst, uncore->regs_bsh, i915_mmio_reg_offset(reg), val);
325 bus_space_write_8(uncore->regs_bst, uncore->regs_bsh, i915_mmio_reg_offset(reg), val)
    [all...]
intel_uncore.c 986 u32 offset = i915_mmio_reg_offset(*reg);
1200 i915_mmio_reg_offset(reg)))
1267 u32 offset = i915_mmio_reg_offset(reg); \
1322 return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1376 u32 offset = i915_mmio_reg_offset(reg); \
1415 return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1481 d->reg_set = i915_mmio_reg_offset(reg_set);
1482 d->reg_ack = i915_mmio_reg_offset(reg_ack);
1484 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
1485 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack)
    [all...]
i915_perf.c 1747 *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
1820 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;
1823 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1824 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));
1838 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;
1841 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1842 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));
1861 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1862 *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
1880 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET))
    [all...]
i915_query.c 195 ret = __put_user(i915_mmio_reg_offset(kernel_regs[r].addr),
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
interrupt.c 159 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
334 regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))
336 regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));
362 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);
368 i915_mmio_reg_offset(up_irq_info->reg_base));
370 i915_mmio_reg_offset(up_irq_info->reg_base));
416 reg_base = i915_mmio_reg_offset(info->reg_base);
474 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
485 reg_base = i915_mmio_reg_offset(info->reg_base);
491 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)
    [all...]
edid.c 382 if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
384 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
410 if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
412 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
414 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
416 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
scheduler.c 97 i915_mmio_reg_offset(EU_PERF_CNTL0),
98 i915_mmio_reg_offset(EU_PERF_CNTL1),
99 i915_mmio_reg_offset(EU_PERF_CNTL2),
100 i915_mmio_reg_offset(EU_PERF_CNTL3),
101 i915_mmio_reg_offset(EU_PERF_CNTL4),
102 i915_mmio_reg_offset(EU_PERF_CNTL5),
103 i915_mmio_reg_offset(EU_PERF_CNTL6),
119 i915_mmio_reg_offset(GEN8_OACTXCONTROL);
225 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
227 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg)
    [all...]
mmio_context.c 226 *cs++ = i915_mmio_reg_offset(mmio->reg);
257 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));
284 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));
539 i915_mmio_reg_offset(mmio->reg),
gvt.h 448 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
452 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
handlers.c 172 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
175 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
536 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {
555 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
637 end = i915_mmio_reg_offset(i915_end);
832 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
835 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
838 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
841 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
1677 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) |
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dsb.c 234 if (reg_val != i915_mmio_reg_offset(reg)) {
246 i915_mmio_reg_offset(reg);
295 i915_mmio_reg_offset(reg);
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_workarounds.c 93 unsigned int addr = i915_mmio_reg_offset(wa->reg);
119 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
121 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
128 i915_mmio_reg_offset(wa_->reg),
147 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
148 i915_mmio_reg_offset(wa_[1].reg));
149 if (i915_mmio_reg_offset(wa_[1].reg) >
150 i915_mmio_reg_offset(wa_[0].reg))
671 *cs++ = i915_mmio_reg_offset(wa->reg);
1003 name, from, i915_mmio_reg_offset(wa->reg)
    [all...]
selftest_workarounds.c 164 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));
191 return i915_mmio_reg_offset(reg);
440 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
494 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
798 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
837 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
896 u32 offset = i915_mmio_reg_offset(reg);
900 i915_mmio_reg_offset(tbl->reg) == offset)
924 i915_mmio_reg_offset(reg), a, b);
946 i915_mmio_reg_offset(reg), a)
    [all...]
selftest_rc6.c 100 *cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO);
selftest_mocs.c 151 u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
190 u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
intel_ring_submission.c 1384 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
1388 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
1393 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
1398 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
1444 *cs++ = i915_mmio_reg_offset(
1499 *cs++ = i915_mmio_reg_offset(last_reg);
1506 *cs++ = i915_mmio_reg_offset(last_reg);
1540 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
intel_rc6.c 719 i = (i915_mmio_reg_offset(reg) -
720 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
intel_mocs.c 436 return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
intel_lrc.c 3113 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
3119 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
3128 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
3195 *batch++ = i915_mmio_reg_offset(lri->reg);
4418 execlists->submit_reg = i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
4419 execlists->ctrl_reg = i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
4424 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
4426 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
4430 execlists->submit_reg = i915_mmio_reg_offset(RING_ELSP(base));
4435 i915_mmio_reg_offset(RING_ELSP(base))
    [all...]
selftest_lrc.c 3776 i915_mmio_reg_offset(RING_START(engine->mmio_base)),
3781 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)),
3786 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)),
3791 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)),
3796 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),
3801 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)),
3877 *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));
3884 *cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/
intel_uc.c 368 i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
371 i915_mmio_reg_offset(GUC_WOPCM_SIZE),
intel_guc.c 72 i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
75 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
  /src/sys/external/bsd/drm2/dist/drm/i915/selftests/
intel_uncore.c 84 u32 offset = i915_mmio_reg_offset(*reg);
  /src/sys/external/bsd/drm2/include/
i915_trace.h 265 uint32_t regoff __trace_used = i915_mmio_reg_offset(reg);
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/
i915_gem_context.c 1127 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
1129 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
1151 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
1153 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));

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