| /src/sys/arch/sparc/include/ |
| instr.h | 212 u_int i_rs1:1; /* source register 1 */ member in struct:instr::__anon0aa89e890708
233 u_int i_rs1:5; /* source register 1 */ member in struct:instr::__anon0aa89e890808
246 u_int i_rs1:5; /* source register 1 */ member in struct:instr::__anon0aa89e890908
260 u_int i_rs1:5; /* source register 1 */ member in struct:instr::__anon0aa89e890a08
268 u_int i_rs1:5; /* source register 1 */ member in struct:instr::__anon0aa89e890b08
277 u_int i_rs1:5; /* source register 1 */ member in struct:instr::__anon0aa89e890c08
296 u_int i_rs1:5; /* source register 1 */ member in struct:instr::__anon0aa89e890d08
321 u_int i_rs1:5; /* source register 1 */ member in struct:instr::__anon0aa89e890f08
|
| /src/sys/arch/sparc/sparc/ |
| emul.c | 162 REGNAME(code->i_op3.i_rs1));
274 if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0) {
297 REGNAME(code.i_op3.i_rs1));
406 if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0) {
|
| /src/sys/arch/sparc64/sparc64/ |
| emul.c | 161 REGNAME(code->i_op3.i_rs1));
271 if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0) {
288 REGNAME(code.i_op3.i_rs1));
398 if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0) {
|
| /src/sys/arch/sparc/fpu/ |
| fpu.c | 337 rs1 = instr.i_opf.i_rs1;
399 rs1 = instr.i_fmovr.i_rs1;
407 rs1 = instr.i_fmovr.i_rs1;
415 rs1 = instr.i_fmovr.i_rs1;
423 rs1 = instr.i_fmovr.i_rs1;
431 rs1 = instr.i_fmovr.i_rs1;
439 rs1 = instr.i_fmovr.i_rs1;
|
| /src/sys/arch/riscv/riscv/ |
| db_machdep.c | 152 return OPCODE_P(insn, JALR) && ri.type_i.i_rs1 == 1;
180 return i.type_i.i_imm11to0 + get_reg_value(tf, i.type_i.i_rs1);
|
| /src/sys/arch/riscv/include/ |
| insn.h | 106 unsigned int i_rs1 : 5; member in struct:riscv_insn::__anon51a8b9bf0708
|
