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    Searched refs:imm6 (Results 1 - 25 of 35) sorted by relevancy

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  /src/sys/arch/aarch64/aarch64/
disasm.c 842 uint64_t sf, uint64_t shift, uint64_t Rm, uint64_t imm6,
846 if ((sf == 0) && (imm6 >= 32)) {
847 UNDEFINED(pc, insn, "illegal imm6");
868 if (imm6 != 0)
869 PRINTF(", %s #%u", DecodeShift(shift), (u_int)imm6);
1130 OP6FUNC(op_add_shiftreg, sf, shift, Rm, imm6, Rn, Rd)
1136 shiftreg_common(di, pc, insn, sf, shift, Rm, imm6, Rn, Rd,
1154 OP6FUNC(op_adds_shiftreg, sf, shift, Rm, imm6, Rn, Rd)
1161 shiftreg_common(di, pc, insn, sf, shift, Rm, imm6, Rn, Rd,
1196 OP6FUNC(op_and_shiftreg, sf, shift, Rm, imm6, Rn, Rd
    [all...]
  /src/external/gpl3/binutils/dist/include/opcode/
cr16.h 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon10627
nds32.h 107 #define N16_TYPE36(op6, rt3, imm6) \
109 | __MF (imm6, 0, 6))
  /src/external/gpl3/binutils.old/dist/include/opcode/
cr16.h 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon12091
nds32.h 107 #define N16_TYPE36(op6, rt3, imm6) \
109 | __MF (imm6, 0, 6))
  /src/external/gpl3/gdb.old/dist/include/opcode/
cr16.h 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon21479
nds32.h 107 #define N16_TYPE36(op6, rt3, imm6) \
109 | __MF (imm6, 0, 6))
  /src/external/gpl3/gdb/dist/include/opcode/
cr16.h 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon1067
nds32.h 107 #define N16_TYPE36(op6, rt3, imm6) \
109 | __MF (imm6, 0, 6))
  /src/external/gpl3/binutils/dist/opcodes/
cr16-opc.c 147 SHIFT_INST_A("ashud", 0x26, 0x48, 25, imm6, regp),
157 SHIFT_INST_L("lshd", 0x25, 0x47, 25, imm6, regp),
559 {6, arg_ic, OP_SIGNED}, /* imm6 */
arm-dis.c 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
5941 unsigned long imm6 = arm_decode_field (given, 16, 21);
5942 if ((imm6 & 0x20) == 0)
5949 && ((imm6 & 0x30) == 0x20))
6933 reason = "invalid imm6";
6937 reason = "fsi = 0 and invalid imm6";
7741 unsigned imm6 = (given & 0x3f0000) >> 16;
7744 imm6 &= 0x1f;
7747 if ((imm6 & 0x20) != 0
5940 unsigned long imm6 = arm_decode_field (given, 16, 21); local
7740 unsigned imm6 = (given & 0x3f0000) >> 16; local
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
cr16-opc.c 147 SHIFT_INST_A("ashud", 0x26, 0x48, 25, imm6, regp),
157 SHIFT_INST_L("lshd", 0x25, 0x47, 25, imm6, regp),
559 {6, arg_ic, OP_SIGNED}, /* imm6 */
arm-dis.c 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
5941 unsigned long imm6 = arm_decode_field (given, 16, 21);
5942 if ((imm6 & 0x20) == 0)
5949 && ((imm6 & 0x30) == 0x20))
6933 reason = "invalid imm6";
6937 reason = "fsi = 0 and invalid imm6";
7741 unsigned imm6 = (given & 0x3f0000) >> 16;
7744 imm6 &= 0x1f;
7747 if ((imm6 & 0x20) != 0
5940 unsigned long imm6 = arm_decode_field (given, 16, 21); local
7740 unsigned imm6 = (given & 0x3f0000) >> 16; local
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
cr16-opc.c 147 SHIFT_INST_A("ashud", 0x26, 0x48, 25, imm6, regp),
157 SHIFT_INST_L("lshd", 0x25, 0x47, 25, imm6, regp),
559 {6, arg_ic, OP_SIGNED}, /* imm6 */
arm-dis.c 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
5941 unsigned long imm6 = arm_decode_field (given, 16, 21);
5942 if ((imm6 & 0x20) == 0)
5949 && ((imm6 & 0x30) == 0x20))
6933 reason = "invalid imm6";
6937 reason = "fsi = 0 and invalid imm6";
7741 unsigned imm6 = (given & 0x3f0000) >> 16;
7744 imm6 &= 0x1f;
7747 if ((imm6 & 0x20) != 0
5940 unsigned long imm6 = arm_decode_field (given, 16, 21); local
7740 unsigned imm6 = (given & 0x3f0000) >> 16; local
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
cr16-opc.c 147 SHIFT_INST_A("ashud", 0x26, 0x48, 25, imm6, regp),
157 SHIFT_INST_L("lshd", 0x25, 0x47, 25, imm6, regp),
559 {6, arg_ic, OP_SIGNED}, /* imm6 */
arm-dis.c 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
5941 unsigned long imm6 = arm_decode_field (given, 16, 21);
5942 if ((imm6 & 0x20) == 0)
5949 && ((imm6 & 0x30) == 0x20))
6933 reason = "invalid imm6";
6937 reason = "fsi = 0 and invalid imm6";
7741 unsigned imm6 = (given & 0x3f0000) >> 16;
7744 imm6 &= 0x1f;
7747 if ((imm6 & 0x20) != 0
5940 unsigned long imm6 = arm_decode_field (given, 16, 21); local
7740 unsigned imm6 = (given & 0x3f0000) >> 16; local
    [all...]
  /src/external/gpl3/binutils/dist/gas/config/
bfin-parse.y 215 #define imm6(x) EXPR_VALUE (x)
1984 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
2119 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2172 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2173 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2196 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2340 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2341 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2351 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
bfin-parse.c 266 #define imm6(x) EXPR_VALUE (x) macro
4410 (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0 ? 1 : 2, 0);
4567 (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
4636 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
4637 (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 1, IS_A1 ((yyvsp[-3].reg)));
4663 (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), -imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
4841 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
4842 (yyval.instr) = DSP32SHIFTIMM (3, 0, imm6 ((yyvsp[0].expr)), 0, 2, IS_A1 ((yyvsp[-4].reg)));
4855 (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 3, IS_A1 ((yyvsp[-5].reg)));
  /src/external/gpl3/binutils.old/dist/gas/config/
bfin-parse.y 215 #define imm6(x) EXPR_VALUE (x)
1984 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
2119 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2172 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2173 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2196 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2340 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2341 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2351 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
  /src/external/gpl3/gdb.old/dist/sim/arm/
thumbemu.c 194 ARMword imm6; local
203 imm6 = tBITS (0, 5);
208 simm32 = (J1 << 19) | (J2 << 18) | (imm6 << 12) | (imm11 << 1);
  /src/external/gpl3/gdb.old/dist/sim/cr16/
interp.c 131 case imm3: case imm4: case imm5: case imm6:
  /src/external/gpl3/gdb/dist/sim/cr16/
interp.c 131 case imm3: case imm4: case imm5: case imm6:
  /src/external/gpl3/gdb.old/dist/gdb/
mep-tdep.c 1557 /* ADD Rn,imm6 0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */
1715 CORE_ADDR imm6 = ADD_OFFSET (insn);
1717 reg[rn] = pv_add_constant (reg[rn], imm6);
1710 CORE_ADDR imm6 = ADD_OFFSET (insn); local
  /src/external/gpl3/gdb/dist/gdb/
mep-tdep.c 1557 /* ADD Rn,imm6 0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */
1715 CORE_ADDR imm6 = ADD_OFFSET (insn);
1717 reg[rn] = pv_add_constant (reg[rn], imm6);
1710 CORE_ADDR imm6 = ADD_OFFSET (insn); local

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