| /src/sys/arch/aarch64/aarch64/ |
| disasm.c | 677 ValidBitMasks(uint64_t sf, uint64_t n, uint64_t imms, uint64_t immr)
697 DecodeBitMasks(uint64_t sf, uint64_t n, uint64_t imms, uint64_t immr)
706 immr &= (esize - 1);
707 result = rotate(esize, (1ULL << (imms + 1)) - 1, immr);
718 MoveWidePreferred(uint64_t sf, uint64_t n, uint64_t imms, uint64_t immr)
721 uint64_t x = DecodeBitMasks(sf, n, imms, immr);
746 if ((sf == 0) && ((n != 0) || (immr > 0x1f)))
749 return ((-immr & 15) <= (15 - imms));
751 return ((immr & 15) <= (imms - (bitwidth - 15)));
757 BFXPreferred(uint64_t sf, uint64_t opc, uint64_t imms, uint64_t immr)
[all...] |
| db_trace.c | 218 DecodeBitMasks(uint64_t sf, uint64_t n, uint64_t imms, uint64_t immr)
227 immr &= (esize - 1);
228 result = rotate(esize, (1ULL << (imms + 1)) - 1, immr);
349 uint64_t immr = (insn >> 16) & 0x3f; local
351 uint64_t v = DecodeBitMasks(1, n, imms, immr);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64InstPrinter.cpp | 121 int64_t immr = Op2.getImm(); local
123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
127 ((imms + 1 == immr))) {
132 shift = immr;
135 shift = immr;
138 shift = immr;
141 shift = immr;
171 int ImmR = MI->getOperand(3).getImm();
175 (ImmR == 0 || ImmS < ImmR) &
[all...] |
| AArch64AddressingModes.h | 212 /// the form N:immr:imms.
252 // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
256 unsigned Immr = (Size - I) & (Size - 1);
269 Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
291 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
294 // Extract the N, imms, and immr fields.
296 unsigned immr = (val >> 6) & 0x3f; local
303 unsigned R = immr & (size - 1);
319 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| aarch64-dis.c | 747 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
945 /* value is N:immr:imms. */
3034 /* When <imms> >= <immr>, the instruction written:
3042 int64_t immr, imms;
3044 immr = inst->operands[2].imm.value;
3046 if (imms >= immr)
3048 int64_t lsb = immr;
3061 /* When <imms> < <immr>, the instruction written:
3069 int64_t immr, imms, val;
3071 immr = inst->operands[2].imm.value
3040 int64_t immr, imms; local
3067 int64_t immr, imms, val; local
3094 int64_t immr, imms, val; local
3133 int64_t immr = inst->operands[2].imm.value; local
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| aarch64-dis.c | 746 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
944 /* value is N:immr:imms. */
3011 /* When <imms> >= <immr>, the instruction written:
3019 int64_t immr, imms;
3021 immr = inst->operands[2].imm.value;
3023 if (imms >= immr)
3025 int64_t lsb = immr;
3038 /* When <imms> < <immr>, the instruction written:
3046 int64_t immr, imms, val;
3048 immr = inst->operands[2].imm.value
3016 int64_t immr, imms; local
3043 int64_t immr, imms, val; local
3070 int64_t immr, imms, val; local
3109 int64_t immr = inst->operands[2].imm.value; local
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| aarch64-dis.c | 746 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
944 /* value is N:immr:imms. */
2985 /* When <imms> >= <immr>, the instruction written:
2993 int64_t immr, imms;
2995 immr = inst->operands[2].imm.value;
2997 if (imms >= immr)
2999 int64_t lsb = immr;
3012 /* When <imms> < <immr>, the instruction written:
3020 int64_t immr, imms, val;
3022 immr = inst->operands[2].imm.value
2990 int64_t immr, imms; local
3017 int64_t immr, imms, val; local
3044 int64_t immr, imms, val; local
3083 int64_t immr = inst->operands[2].imm.value; local
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| aarch64-dis.c | 744 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
942 /* value is N:immr:imms. */
3010 /* When <imms> >= <immr>, the instruction written:
3018 int64_t immr, imms;
3020 immr = inst->operands[2].imm.value;
3022 if (imms >= immr)
3024 int64_t lsb = immr;
3037 /* When <imms> < <immr>, the instruction written:
3045 int64_t immr, imms, val;
3047 immr = inst->operands[2].imm.value
3015 int64_t immr, imms; local
3042 int64_t immr, imms, val; local
3069 int64_t immr, imms, val; local
3108 int64_t immr = inst->operands[2].imm.value; local
[all...] |
| /src/external/gpl3/gdb.old/dist/gdbserver/ |
| linux-aarch64-low.cc | 1842 SBFM rd, rn, #immr, #imms
1844 This instruction moves the bits from #immr to #imms into the
1849 IMMR is the bit number to start at (least significant bit).
1854 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1859 return aarch64_emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16)
1887 UBFM rd, rn, #immr, #imms
1889 This instruction moves the bits from #immr to #imms into the
1894 IMMR is the bit number to start at (least significant bit).
1899 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1904 return aarch64_emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16
[all...] |
| /src/external/gpl3/gdb/dist/gdbserver/ |
| linux-aarch64-low.cc | 1888 SBFM rd, rn, #immr, #imms
1890 This instruction moves the bits from #immr to #imms into the
1895 IMMR is the bit number to start at (least significant bit).
1900 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1905 return aarch64_emit_insn (buf, SBFM | size | n | ENCODE (immr, 6, 16)
1933 UBFM rd, rn, #immr, #imms
1935 This instruction moves the bits from #immr to #imms into the
1940 IMMR is the bit number to start at (least significant bit).
1945 struct aarch64_register rn, uint32_t immr, uint32_t imms)
1950 return aarch64_emit_insn (buf, UBFM | size | n | ENCODE (immr, 6, 16
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| simulator.c | 144 /* Instr[22,10] encodes N immr and imms. we want a lookup table
157 uint32_t immr = uimm (index, 11, 6); local
160 LITable [index] = expand_logical_immediate (imms, immr, n);
9921 instr[21,16] = immr
9929 /* uint32_t immr = INSTR (21, 16);. */
10332 instr[21,16] = immr : 0xxxxx for 32 bit, xxxxxx for 64 bit
10342 /* 32 bit operations must have immr[5] = 0 and imms[5] = 0. */
10344 uint32_t immr = INSTR (21, 16); local
10349 if (!size && uimm (immr, 5, 5))
10360 case 0: sbfm32 (cpu, immr, imms); return
[all...] |
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| simulator.c | 144 /* Instr[22,10] encodes N immr and imms. we want a lookup table
157 uint32_t immr = uimm (index, 11, 6); local
160 LITable [index] = expand_logical_immediate (imms, immr, n);
9921 instr[21,16] = immr
9929 /* uint32_t immr = INSTR (21, 16);. */
10332 instr[21,16] = immr : 0xxxxx for 32 bit, xxxxxx for 64 bit
10342 /* 32 bit operations must have immr[5] = 0 and imms[5] = 0. */
10344 uint32_t immr = INSTR (21, 16); local
10349 if (!size && uimm (immr, 5, 5))
10360 case 0: sbfm32 (cpu, immr, imms); return
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 1855 SDValue &Opd0, unsigned &Immr,
1882 Immr = ShiftImm;
1934 unsigned &Immr, unsigned &Imms,
1948 if (isSeveralBitsExtractOpFromShr(N, Opc, Opd0, Immr, Imms))
1989 int immr = SrlImm - ShlImm; local
1990 Immr = immr < 0 ? immr + VT.getSizeInBits() : immr;
2016 unsigned Immr = ShiftImm
[all...] |
