| /src/sys/arch/aarch64/include/ |
| db_machdep.h | 89 #define BKPT_SET(insn, addr) (BKPT_INSN)
109 inst_return(db_expr_t insn)
111 LE32TOH(insn);
112 return ((insn & 0xfffffc1f) == 0xd65f0000); /* ret xN */
116 inst_trap_return(db_expr_t insn)
118 LE32TOH(insn);
119 return insn == 0xd69f03e0; /* eret */
123 inst_call(db_expr_t insn)
125 LE32TOH(insn);
126 return ((insn & 0xfc000000) == 0x94000000) /* bl *
[all...] |
| /src/sys/arch/riscv/include/ |
| insn.h | 1 /* $NetBSD: insn.h,v 1.5 2024/02/02 22:00:33 andvar Exp $ */
160 #define INSN_SIZE_IS_16(insn) (((insn) & 0b11) != 0b11)
161 #define INSN_SIZE_IS_32(insn) (((insn) & 0b11100) != 0b11100)
162 #define INSN_SIZE_IS_48(insn) (((insn) & 0b100000) != 0b100000)
163 #define INSN_SIZE_IS_64(insn) (((insn) & 0b1000000) != 0b1000000)
166 #define INSN_HALFWORDS(insn) \
[all...] |
| /src/sys/arch/arm/arm/ |
| disassem.c | 66 * insn[cc][mod] [operands]
435 u_int insn; local in function:disasm
443 di->di_printf("thumb insn\n");
449 insn = di->di_readword(loc);
451 insn = bswap32(insn);
456 /* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/
459 if ((insn & i_ptr->mask) == i_ptr->pattern) {
467 di->di_printf("und%s\t%08x\n", insn_condition(insn), insn)
[all...] |
| /src/sys/arch/or1k/include/ |
| db_machdep.h | 45 #define BKPT_SET(insn, addr) (BKPT_INSN)
63 inst_call(db_expr_t insn)
65 return (insn & 0xfc000000) == 0x04000000 /* l.jal */
66 || (insn & 0xffff07ff) == 0x48000000; /* l.jalr */
70 inst_load(db_expr_t insn)
79 inst_return(db_expr_t insn)
81 return insn == 0x44004800; /* l.jr r9 */
85 inst_store(db_expr_t insn)
93 inst_trap_return(db_expr_t insn)
95 return insn == 0x24000000; /* l.rfe *
[all...] |
| /src/sys/arch/sh3/sh3/ |
| db_disasm.c | 153 uint16_t insn; local in function:get_insn
163 if (ufetch_16(pc, &insn))
167 retval = kcopy(pc, &insn, sizeof(insn));
172 return insn;
178 uint16_t insn = get_insn(pc); local in function:get_opcode
183 n0 = (insn & 0xf000) >> 12;
184 n3 = (insn & 0x000f);
194 uint16_t insn = get_insn(pc); local in function:f_02
197 rn = (insn & 0x0f00) >> 8
244 uint16_t insn = get_insn(pc); local in function:f_03
278 uint16_t insn = get_insn(pc); local in function:f_04
307 uint16_t insn = get_insn(pc); local in function:f_08
355 uint16_t insn = get_insn(pc); local in function:f_09
383 uint16_t insn = get_insn(pc); local in function:f_0a
424 uint16_t insn = get_insn(pc); local in function:f_0b
450 uint16_t insn = get_insn(pc); local in function:f_0c
479 uint16_t insn = get_insn(pc); local in function:f_10
493 uint16_t insn = get_insn(pc); local in function:f_20
519 uint16_t insn = get_insn(pc); local in function:f_24
548 uint16_t insn = get_insn(pc); local in function:f_28
578 uint16_t insn = get_insn(pc); local in function:f_2c
607 uint16_t insn = get_insn(pc); local in function:f_30
633 uint16_t insn = get_insn(pc); local in function:f_34
662 uint16_t insn = get_insn(pc); local in function:f_38
688 uint16_t insn = get_insn(pc); local in function:f_3c
718 uint16_t insn = get_insn(pc); local in function:f_40
742 uint16_t insn = get_insn(pc); local in function:f_41
767 uint16_t insn = get_insn(pc); local in function:f_42
808 uint16_t insn = get_insn(pc); local in function:f_43
857 uint16_t insn = get_insn(pc); local in function:f_44
877 uint16_t insn = get_insn(pc); local in function:f_45
901 uint16_t insn = get_insn(pc); local in function:f_46
942 uint16_t insn = get_insn(pc); local in function:f_47
991 uint16_t insn = get_insn(pc); local in function:f_48
1015 uint16_t insn = get_insn(pc); local in function:f_49
1039 uint16_t insn = get_insn(pc); local in function:f_4a
1080 uint16_t insn = get_insn(pc); local in function:f_4b
1104 uint16_t insn = get_insn(pc); local in function:f_4c
1115 uint16_t insn = get_insn(pc); local in function:f_4d
1126 uint16_t insn = get_insn(pc); local in function:f_4e
1175 uint16_t insn = get_insn(pc); local in function:f_4f
1186 uint16_t insn = get_insn(pc); local in function:f_50
1200 uint16_t insn = get_insn(pc); local in function:f_60
1229 uint16_t insn = get_insn(pc); local in function:f_64
1258 uint16_t insn = get_insn(pc); local in function:f_68
1287 uint16_t insn = get_insn(pc); local in function:f_6c
1316 uint16_t insn = get_insn(pc); local in function:f_70
1328 uint16_t insn = get_insn(pc); local in function:f_80
1409 uint16_t insn = get_insn(pc); local in function:f_90
1422 uint16_t insn = get_insn(pc); local in function:f_a0
1436 uint16_t insn = get_insn(pc); local in function:f_b0
1450 uint16_t insn = get_insn(pc); local in function:f_c0
1549 uint16_t insn = get_insn(pc); local in function:f_d0
1562 uint16_t insn = get_insn(pc); local in function:f_e0
1574 uint16_t insn = get_insn(pc); local in function:f_f0
1603 uint16_t insn = get_insn(pc); local in function:f_f4
1632 uint16_t insn = get_insn(pc); local in function:f_f8
1661 uint16_t insn = get_insn(pc); local in function:f_fc
1673 uint16_t insn = get_insn(pc); local in function:f_fd
1731 uint16_t insn = get_insn(pc); local in function:f_fe
[all...] |
| /src/sys/arch/m68k/fpe/ |
| fpu_fstore.c | 45 fpu_emul_fstore(struct fpemu *fe, struct instruction *insn)
60 word1 = insn->is_word1;
65 insn->is_datasize = 8;
67 insn->is_datasize = 4;
69 insn->is_datasize = 2;
72 insn->is_datasize = 1;
75 insn->is_datasize = 12;
85 format, insn->is_datasize);
91 modreg = insn->is_opcode & 077;
100 sig = fpu_decode_ea(frame, insn, &insn->is_ea, modreg)
[all...] |
| fpu_emulate.c | 70 #define DUMP_INSN(insn) \
71 printf("%s: insn={adv=%d,siz=%d,op=%04x,w1=%04x}\n", \
73 (insn)->is_advance, (insn)->is_datasize, \
74 (insn)->is_opcode, (insn)->is_word1)
77 #define DUMP_INSN(insn) do {} while (/* CONSTCOND */ 0)
89 static struct instruction insn; local in function:fpu_emulate
94 /* initialize insn.is_datasize to tell it is *not* initialized */
95 insn.is_datasize = -1
[all...] |
| fpu_fscale.c | 51 fpu_emul_fscale(struct fpemu *fe, struct instruction *insn)
75 word1 = insn->is_word1;
98 insn->is_datasize = 8;
100 insn->is_datasize = 4;
102 insn->is_datasize = 2;
104 insn->is_datasize = 1;
106 insn->is_datasize = 12;
114 modreg = insn->is_opcode & 077;
120 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode)
[all...] |
| fpu_calcea.c | 71 fpu_decode_ea(struct frame *frame, struct instruction *insn,
77 if (insn->is_datasize < 0)
95 sig = fetch_immed(frame, insn, &ea->ea_immed[0]);
97 __func__, insn->is_datasize));
109 __func__, (void *)ea->ea_fea, insn->is_datasize));
120 if (insn->is_datasize == 12)
150 sig = fetch_disp(frame, insn, 1, &ea->ea_offset);
157 sig = decode_ea6(frame, insn, ea, modreg);
166 sig = fetch_disp(frame, insn, 1,
174 sig = fetch_disp(frame, insn, 2
[all...] |
| /src/sys/arch/arm/include/ |
| trap.h | 73 #define DTRACE_IS_BREAKPOINT(insn) ((insn & DTRACE_BREAKPOINT_MASK) == DTRACE_BREAKPOINT)
|
| locore.h | 208 uint32_t insn; local in function:read_insn
210 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va));
212 insn = *(const uint32_t *)va;
215 insn = bswap32(insn);
217 return insn;
227 uint32_t insn; local in function:read_thumb_insn
230 __asm __volatile("ldrht %0, [%1, #0]" : "=&r"(insn) : "r"(va));
232 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va));
234 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3))
[all...] |
| /src/sys/arch/alpha/alpha/ |
| db_interface.c | 391 alpha_instruction insn; local in function:db_inst_call
393 insn.bits = ins;
394 return ((insn.branch_format.opcode == op_bsr) ||
395 ((insn.jump_format.opcode == op_j) &&
396 (insn.jump_format.action & 1)));
402 alpha_instruction insn; local in function:db_inst_return
404 insn.bits = ins;
405 return ((insn.jump_format.opcode == op_j) &&
406 (insn.jump_format.action == op_ret));
412 alpha_instruction insn; local in function:db_inst_trap_return
422 alpha_instruction insn; local in function:db_inst_branch
451 alpha_instruction insn; local in function:db_inst_unconditional_flow_transfer
486 alpha_instruction insn; local in function:db_inst_load
516 alpha_instruction insn; local in function:db_inst_store
545 alpha_instruction insn; local in function:db_branch_taken
[all...] |
| db_disasm.c | 828 opcode = op_name[ctx->insn.mem_format.opcode];
834 switch (ctx->insn.mem_format.opcode) {
838 pal_opname(ctx->insn.pal_format.function));
860 opcode = arit_name(ctx->insn.operate_lit_format.function);
864 opcode = logical_name(ctx->insn.operate_lit_format.function);
868 opcode = bitop_name(ctx->insn.operate_lit_format.function);
872 opcode = mul_name(ctx->insn.operate_lit_format.function);
878 register_name(ctx, ctx->insn.operate_lit_format.ra));
879 if (ctx->insn.operate_lit_format.one) {
881 ctx->insn.operate_lit_format.literal)
[all...] |
| /src/sys/arch/riscv/riscv/ |
| db_disasm.c | 41 #include <riscv/insn.h>
135 db_disasm_16(db_addr_t loc, uint32_t insn, bool altfmt)
137 /* note: insn needs to be uint32_t for immediate computations */
142 switch (COMBINE(INSN16_FUNCT3(insn), INSN16_QUADRANT(insn))) {
144 rd = INSN16_RS2x(insn);
145 imm = INSN16_IMM_CIW(insn);
153 rs1 = INSN16_RS1x(insn);
154 rd = INSN16_RS2x(insn);
156 imm = INSN16_IMM_CL_D(insn);
1447 uint16_t insn[5]; local in function:db_disasm
[all...] |
| db_machdep.c | 41 #include <riscv/insn.h>
126 inst_branch(uint32_t insn)
128 return OPCODE_P(insn, BRANCH);
133 inst_call(uint32_t insn)
135 const union riscv_insn ri = { .val = insn };
136 return (OPCODE_P(insn, JAL) && ri.type_u.u_rd == 1)
137 || (OPCODE_P(insn, JALR) && ri.type_i.i_rd == 1);
142 inst_unconditional_flow_transfer(uint32_t insn)
145 return OPCODE_P(insn, JAL) || OPCODE_P(insn, JALR)
[all...] |
| /src/sys/arch/mips/mips/ |
| mips_fixup.c | 90 const uint32_t insn = *insnp; local in function:mips_fixup_exceptions
91 if (INSN_LUI_P(insn)) {
92 const int32_t offset = insn << 16;
93 lui_reg = (insn >> 16) & 31;
95 printf("%s: %#x: insn %08x: lui r%zu, %%hi(%#x)",
97 insn, lui_reg, offset);
102 lui_insn = insn;
116 && (INSN_LOAD_P(insn) || INSN_STORE_P(insn))) {
117 size_t base = (insn >> 21) & 31
244 uint32_t insn = *insnp; local in function:fixup_mips_jump
317 const InstFmt insn = { .word = stubp[n] }; local in function:mips_fixup_addr
487 uint32_t insn = *insnp; local in function:mips_fixup_stubs
[all...] |
| kobj_machdep.c | 70 uint32_t *insn; local in function:kobj_reloc
94 insn = (void *)where;
129 KASSERT((*insn & 0x3ffffff) == 0);
130 DPRINTF(" orig insn = 0x%08x\n", *insn);
131 *insn |= addr;
132 DPRINTF(" new insn = 0x%08x\n", *insn);
142 KASSERT((*insn & 0xffff) == 0);
143 DPRINTF(" orig insn = 0x%08x\n", *insn)
[all...] |
| /src/sys/arch/powerpc/powerpc/ |
| fix_unaligned.c | 37 * - Fetch and decode insn; 403 does not have DSISR.
39 * - Only for integer insn; unaligned floating-point load/store are taken
40 * care of by FPU emulator. (Support for FPU insn should be trivial.)
133 #define DISASM(tf, insn) \
136 opc_disasm((tf)->tf_srr0, (insn)->i_int); \
139 #define DISASM(tf, insn) __nothing
152 union instr insn; local in function:fix_unaligned
157 ret = ufetch_32((uint32_t *)tf->tf_srr0, (uint32_t *)&insn.i_int);
169 if (emul_unaligned(tf, ksi, &insn))
172 CTASSERT(sizeof(insn) == 4); /* It was broken before... *
[all...] |
| process_machdep.c | 292 ppc_ifetch(struct lwp *l, vaddr_t va, uint32_t *insn)
297 iov.iov_base = insn;
298 iov.iov_len = sizeof(*insn);
302 uio.uio_resid = sizeof(*insn);
310 ppc_istore(struct lwp *l, vaddr_t va, uint32_t insn)
315 iov.iov_base = &insn;
316 iov.iov_len = sizeof(insn);
320 uio.uio_resid = sizeof(insn);
339 uint32_t insn; local in function:ppc_sstep
353 if ((rv = ppc_ifetch(l, va[0], &insn)) != 0
[all...] |
| /src/common/lib/libc/arch/powerpc/atomic/ |
| atomic_op_asm.h | 47 #define ATOMIC_OP_32_ARG(op,insn,arg) \
51 insn %r5,%r3,arg ; \
59 #define ATOMIC_OP_64_ARG(op,insn,arg) \
63 insn %r5,%r3,arg ; \
70 #define ATOMIC_OP_32_ARG_NV(op,insn,arg) \
74 insn %r3,%r3,arg ; \
82 #define ATOMIC_OP_64_ARG_NV(op,insn,arg) \
86 insn %r3,%r3,arg ; \
|
| /src/sys/arch/sparc/sparc/ |
| db_interface.c | 478 union instr insn; local in function:db_branch_taken
481 insn.i_int = inst;
487 if (insn.i_any.i_op != IOP_OP2 || insn.i_branch.i_annul != 1)
490 switch (insn.i_op2.i_op2) {
497 switch (insn.i_branch.i_cond)
524 union instr insn; local in function:db_inst_branch
526 insn.i_int = inst;
528 if (insn.i_any.i_op != IOP_OP2)
531 switch (insn.i_op2.i_op2)
549 union instr insn; local in function:db_inst_call
569 union instr insn; local in function:db_inst_unconditional_flow_transfer
605 union instr insn; local in function:db_inst_trap_return
617 union instr insn; local in function:db_inst_load
657 union instr insn; local in function:db_inst_store
[all...] |
| db_disasm.c | 64 * operation is encoded into a particular 32-bit insn. There are 3
66 * bits 30-31 of the insn. Here are the bit fields and their names:
177 s -- %asi is implicit in the insn, rs1 value not used
184 9 -- logical or of the cmask and mmask fields (membar insn)
883 unsigned int insn, you_lose, bitmask; local in function:db_disasm
889 insn = db_get_value(loc, 4, 0);
891 if (insn == 0x01000000) {
937 if (((bitmask & insn) == bitmask) && ((you_lose & insn) == 0)) {
958 if (insn & A(1)
[all...] |
| /src/sys/arch/mips/include/ |
| mips_opcode.h | 419 #define INSN_LUI_P(insn) (((insn) >> 26) == OP_LUI)
420 #define INSN_LW_P(insn) (((insn) >> 26) == OP_LW)
421 #define INSN_SW_P(insn) (((insn) >> 26) == OP_SW)
422 #define INSN_LD_P(insn) (((insn) >> 26) == OP_LD)
423 #define INSN_SD_P(insn) (((insn) >> 26) == OP_SD
[all...] |
| /src/sys/arch/aarch64/aarch64/ |
| db_trace.c | 295 uint32_t insn; variable in typeref:typename:uint32_t
297 db_read_bytes(pc, sizeof(insn), (char *)&insn);
298 if (insn == 0)
300 LE32TOH(insn);
302 TRACE_DEBUG("INSN: %016lx: %04x\n", pc, insn);
306 insn == 0xd65f03e0 || /* "ret" */
307 insn == 0xd69f03e0 || /* "eret" */
308 insn == 0xd503233f)) /* "paciasp" *
[all...] |
| kobj_machdep.c | 130 uint32_t *insn, immhi, immlo, shift; local in function:kobj_reloc
162 insn = (uint32_t *)where;
193 le32toh(*insn), strdisasm((vaddr_t)insn, 0));
256 *insn = htole32(
257 (le32toh(*insn) & ~__BITS(21,10)) | (val << 10));
278 *insn = htole32((le32toh(*insn) &
302 *insn = htole32((le32toh(*insn) & ~__BITS(25,0)) | val)
[all...] |
