| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| axp152.dtsi | 47 interrupt-controller;
48 #interrupt-cells = <1>;
|
| axp809.dtsi | 51 interrupt-controller;
52 #interrupt-cells = <1>;
|
| arm-realview-eb.dts | 24 #include <dt-bindings/interrupt-controller/irq.h>
51 intc: interrupt-controller@10040000 {
53 #interrupt-cells = <3>;
55 interrupt-controller;
63 * This adapts all the peripherals to the interrupt routing
68 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
83 interrupt-parent = <&intc>;
89 interrupt-parent = <&intc>
[all...] |
| arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
47 interrupt-affinity = <&cpu0>;
50 /* Primary GIC PL390 interrupt controller in the test chip */
51 intc: interrupt-controller@1e000000 {
53 #interrupt-cells = <3>;
55 interrupt-controller;
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>
[all...] |
| arm-realview-eb-mp.dtsi | 23 #include <dt-bindings/interrupt-controller/irq.h>
40 /* Primary interrupt controller in the test chip */
41 intc: interrupt-controller@1f000100 {
43 #interrupt-cells = <3>;
45 interrupt-controller;
50 /* Secondary interrupt controller on the FPGA */
51 intc_second: interrupt-controller@10040000 {
53 #interrupt-cells = <3>;
55 interrupt-controller;
58 interrupt-parent = <&intc>
[all...] |
| arm-realview-pbx-a9.dts | 89 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
105 interrupt-affinity = <&CPU0>, <&CPU1>;
108 /* Primary GIC PL390 interrupt controller in the test chip */
109 intc: interrupt-controller@1f000000 {
111 #interrupt-cells = <3>;
113 interrupt-controller;
120 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>
[all...] |
| vf500.dtsi | 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
28 intc: interrupt-controller@40003000 {
30 #interrupt-cells = <3>;
31 interrupt-controller;
32 interrupt-parent = <&intc>;
41 interrupt-parent = <&intc>;
50 interrupt-affinity = <&a5_cpu>;
59 interrupt-parent = <&intc>;
|
| armv7-m.dtsi | 3 nvic: interrupt-controller@e000e100 {
5 interrupt-controller;
6 #interrupt-cells = <1>;
20 interrupt-parent = <&nvic>;
|
| sun5i-a13-empire-electronix-m712.dts | 46 #include <dt-bindings/interrupt-controller/irq.h>
|
| vf610m4.dtsi | 56 interrupt-parent = <&nvic>;
|
| /src/usr.bin/make/unit-tests/ |
| cmd-interrupt.exp | 1 > cmd-interrupt-ordinary
2 make: *** cmd-interrupt-ordinary removed
3 interrupt-ordinary: ok
4 > cmd-interrupt-phony
5 interrupt-phony: ok
6 > cmd-interrupt-precious
7 interrupt-precious: ok
8 interrupt-compat expected-fail
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/interrupt-controller/ |
| mips-gic.h | 7 #include <dt-bindings/interrupt-controller/irq.h>
|
| apple-aic.h | 7 #include <dt-bindings/interrupt-controller/irq.h>
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/ |
| foundation-v8-gicv2.dtsi | 8 gic: interrupt-controller@2c001000 {
10 #interrupt-cells = <3>;
12 interrupt-controller;
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/loongson/ |
| loongson64-2k1000.dtsi | 5 #include <dt-bindings/interrupt-controller/irq.h>
40 cpuintc: interrupt-controller {
42 #interrupt-cells = <1>;
43 interrupt-controller;
44 compatible = "mti,cpu-interrupt-controller";
55 liointc0: interrupt-controller@1fe11400 {
62 interrupt-controller;
63 #interrupt-cells = <2>;
65 interrupt-parent = <&cpuintc>;
67 interrupt-names = "int0"
[all...] |
| loongson64c-package.dtsi | 3 #include <dt-bindings/interrupt-controller/irq.h>
9 cpuintc: interrupt-controller {
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
27 liointc: interrupt-controller@3ff01400 {
31 interrupt-controller;
32 #interrupt-cells = <2>;
34 interrupt-parent = <&cpuintc>;
36 interrupt-names = "int0", "int1"
[all...] |
| loongson64g-package.dtsi | 3 #include <dt-bindings/interrupt-controller/irq.h>
9 cpuintc: interrupt-controller {
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
24 liointc: interrupt-controller@3ff01400 {
28 interrupt-controller;
29 #interrupt-cells = <2>;
31 interrupt-parent = <&cpuintc>;
33 interrupt-names = "int0", "int1"
[all...] |
| loongson64c_4core_ls7a.dts | 13 htvec: interrupt-controller@efdfb000080 {
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
31 interrupt-controller;
35 interrupt-parent = <&htvec>;
|
| loongson64g_4core_ls7a.dts | 13 htvec: interrupt-controller@efdfb000080 {
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
35 interrupt-controller;
39 interrupt-parent = <&htvec>;
|
| ls7a-pch.dtsi | 13 pic: interrupt-controller@10000000 {
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
19 #interrupt-cells = <2>;
26 interrupt-parent = <&pic>;
36 interrupt-parent = <&pic>;
46 interrupt-parent = <&pic>;
56 interrupt-parent = <&pic>;
66 #interrupt-cells = <2>;
83 interrupt-parent = <&pic>
[all...] |
| loongson64c_4core_rs780e.dts | 13 htpic: interrupt-controller@efdfb000080 {
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
|
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/mti/ |
| malta.dts | 4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/mips-gic.h>
16 cpu_intc: interrupt-controller {
17 compatible = "mti,cpu-interrupt-controller";
19 interrupt-controller;
20 #interrupt-cells = <1>;
23 gic: interrupt-controller@1bdc0000 {
27 interrupt-controller;
28 #interrupt-cells = <3>;
31 * Declare the interrupt-parent even though the mti,gi
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/brcm/ |
| bcm7125.dtsi | 30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller
[all...] |
| bcm7360.dtsi | 24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/img/ |
| boston.dts | 6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
46 #interrupt-cells = <1>;
48 interrupt-parent = <&gic>;
56 interrupt-map-mask = <0 0 0 7>;
57 interrupt-map = <0 0 0 1 &pci0_intc 1>,
62 pci0_intc: interrupt-controller {
63 interrupt-controller;
65 #interrupt-cells = <1>;
76 #interrupt-cells = <1>
[all...] |
