| /src/sys/arch/arm/xscale/ |
| becc_intr.h | 51 extern volatile uint32_t intr_enabled;
55 * (disabled), so we must invert our intr_enabled mask.
58 BECC_CSR_WRITE(BECC_ICMR, ~intr_enabled & ICU_VALID_MASK);
76 extern volatile uint32_t intr_enabled, becc_ipending;
90 intr_enabled |= hwpend;
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| i80321_intr.h | 55 extern volatile uint32_t intr_enabled;
59 : "r" (intr_enabled & ICU_INT_HWMASK));
63 extern volatile uint32_t intr_enabled;
80 intr_enabled |= hwpend;
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| ixp425_intr.h | 56 extern volatile uint32_t intr_enabled;
58 IXPREG(IXP425_INT_ENABLE) = intr_enabled & IXP425_INT_HWMASK;
65 extern volatile uint32_t intr_enabled;
77 intr_enabled |= hwpend;
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| becc_icu.c | 76 volatile uint32_t intr_enabled; variable
134 return (icsr & intr_enabled);
149 intr_enabled |= (1U << irq);
157 intr_enabled &= ~(1U << irq);
247 intr_enabled = 0; /* All interrupts disabled */
270 intr_enabled = 0;
350 intr_enabled &= ~hwpend;
383 intr_enabled |= ibit;
388 intr_enabled |= (becc_ipending & ~imask);
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| i80321_icu.c | 73 volatile uint32_t intr_enabled; variable
131 return (iintsrc & intr_enabled);
147 intr_enabled |= (1U << irq);
155 intr_enabled &= ~(1U << irq);
228 intr_enabled = 0; /* All interrupts disabled */
247 intr_enabled = 0;
369 intr_enabled &= ~hwpend;
444 intr_enabled |= ibit;
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| ixp425_intr.c | 97 volatile uint32_t intr_enabled; variable
140 return IXPREG(IXP425_INT_STATUS) & intr_enabled;
153 intr_enabled |= (1U << irq);
161 intr_enabled &= ~(1U << irq);
285 intr_enabled = 0; /* All interrupts disabled */
304 intr_enabled = 0;
400 intr_enabled &= ~hwpend;
446 intr_enabled |= ibit;
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| /src/sys/arch/evbarm/ifpga/ |
| ifpga_intr.h | 55 extern volatile uint32_t intr_enabled;
57 uint32_t mask = intr_enabled;
68 extern volatile uint32_t intr_enabled;
79 intr_enabled |= hwpend;
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| ifpga_intr.c | 67 volatile uint32_t intr_enabled; variable
125 intr_enabled |= (1U << irq);
133 intr_enabled &= ~(1U << irq);
228 intr_enabled = 0;
312 intr_enabled &= ~hwpend;
351 intr_enabled |= ibit;
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| /src/sys/arch/arm/footbridge/ |
| footbridge_intr.h | 86 extern volatile uint32_t intr_enabled;
91 uint32_t tmp = intr_enabled & ICU_INT_HWMASK;
101 extern volatile uint32_t intr_enabled;
113 intr_enabled |= hwpend;
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| footbridge_irqhandler.c | 70 volatile uint32_t intr_enabled; variable
94 intr_enabled |= (1U << irq);
101 intr_enabled &= ~(1U << irq);
191 intr_enabled = 0;
295 intr_enabled &= ~hwpend;
331 intr_enabled |= ibit;
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| /src/sys/arch/evbarm/iq80310/ |
| iq80310_intr.c | 75 uint32_t intr_enabled; variable
109 return (intstat & intr_enabled);
117 intr_enabled |= IRQ_BITS_ALWAYS_ON;
120 disabled = (~intr_enabled) & IRQ_BITS;
129 intr_enabled |= (1U << irq);
137 intr_enabled &= ~(1U << irq);
334 intr_enabled |= IRQ_BITS_ALWAYS_ON;
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| /src/sys/arch/arm/ixp12x0/ |
| ixp12x0_intr.c | 70 volatile uint32_t intr_enabled; variable
123 intr_enabled |= (1U << irq);
145 intr_enabled ^= ~(1U << irq);
309 intr_enabled = 0;
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| /src/sys/arch/sparc64/sparc64/ |
| intr.c | 405 sun4v_intr_setenabled(uint64_t devhandle, uint64_t ino, uint64_t intr_enabled)
408 ("%s: devhandle %#lx ino %#lx intr_enabled %#lx\n",
409 __func__, devhandle, ino, intr_enabled));
413 return hv_intr_setenabled(ino, intr_enabled);
415 return hv_vintr_setenabled(devhandle, ino, intr_enabled);
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| /src/sys/arch/sparc64/include/ |
| hypervisor.h | 132 int64_t hv_intr_getenabled(uint64_t sysino, uint64_t *intr_enabled);
133 int64_t hv_intr_setenabled(uint64_t sysino, uint64_t intr_enabled);
141 #define INTR_ENABLED 1
153 uint64_t *intr_enabled);
155 uint64_t intr_enabled);
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