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  /src/sys/arch/mipsco/mipsco/
interrupt.c 46 uint32_t ipending; local in function:cpu_intr
51 while (ppl < (ipl = splintr(&ipending))) {
53 (*platform.iointr)(status, pc, ipending);
mips_3x30.c 101 if (ipending & (mask)) { \
107 pizazz_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
110 if (ipending & MIPS_INT_MASK_2) { /* Timer Interrupt */
121 if (ipending & MIPS_INT_MASK_5) /* level 5 interrupt */
130 if (ipending & INT_MASK_FPU) {
  /src/sys/arch/emips/emips/
interrupt.c 100 uint32_t ipending; local in function:cpu_intr
118 while (ppl < (ipl = splintr(&ipending))) {
121 if (ipending & MIPS_INT_MASK_5) {
122 (*platform.iointr)(status, pc, ipending);
127 ipl = splintr(&ipending);
130 if (ipending & MIPS_INT_MASK_5) {
131 (*platform.iointr)(status, pc, ipending);
140 emips_aic_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
148 ipending = TheAic->IrqStatus;
150 while (ipending) {
    [all...]
  /src/sys/arch/mips/mips/
mips_softint.c 108 softint_process(uint32_t ipending)
113 KASSERT((ipending & MIPS_SOFT_INT_MASK) != 0);
114 KASSERT((ipending & ~MIPS_SOFT_INT_MASK) == 0);
121 if (ipending & MIPS_SOFT_INT_MASK_0) {
126 ipending |= MIPS_SOFT_INT_MASK_1;
128 KASSERT(ipending & MIPS_SOFT_INT_MASK_1);
145 _clrsoftintr(ipending);
  /src/sys/arch/arc/arc/
interrupt.c 99 uint32_t ipending; local in function:cpu_intr
109 while (ppl < (ipl = splintr(&ipending))) {
111 if (ipending & MIPS_INT_MASK_5) {
124 if (inttab->int_mask & ipending) {
125 (*inttab->int_hand)(ipending, &cf);
135 if (inttab->int_mask & ipending) {
136 (*inttab->int_hand)(ipending, &cf);
  /src/sys/arch/evbmips/atheros/
mach_intr.c 58 evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
61 (*platformsw->apsw_intrsw->aisw_iointr)(ipl, cf->pc, ipending);
  /src/sys/arch/evbmips/alchemy/
mach_intr.c 63 evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
66 au_iointr(ipl, cf->pc, ipending);
  /src/sys/arch/evbmips/cavium/
mach_intr.c 63 evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
66 octeon_iointr(ipl, cf->pc, ipending);
  /src/sys/arch/newsmips/newsmips/
news4000.c 79 uint32_t ipending; local in function:news4000_intr
82 while (ppl < (ipl = splintr(&ipending))) {
83 if (ipending & MIPS_INT_MASK_2) {
103 if (ipending & MIPS_INT_MASK_5) {
110 if (ipending & MIPS_INT_MASK_4) {
117 if (ipending & MIPS_INT_MASK_3) {
122 if (ipending & MIPS_INT_MASK_1) {
127 if (ipending & MIPS_INT_MASK_0) {
news5000.c 84 uint32_t ipending; local in function:news5000_intr
87 while (ppl < (ipl = splintr(&ipending))) {
89 if (ipending & MIPS_INT_MASK_2) {
122 if (ipending & MIPS_INT_MASK_5) {
131 if (ipending & MIPS_INT_MASK_4) {
159 if (ipending & MIPS_INT_MASK_3) {
168 if (ipending & MIPS_INT_MASK_1) {
173 if (ipending & MIPS_INT_MASK_0) {
news3400.c 88 uint32_t ipending; local in function:news3400_intr
91 while (ppl < (ipl = splintr(&ipending))) {
94 if (ipending & MIPS_INT_MASK_2) {
116 if (ipending & MIPS_INT_MASK_5) {
122 if (ipending & MIPS_INT_MASK_4) {
127 if (ipending & MIPS_INT_MASK_1) {
131 if (ipending & MIPS_INT_MASK_0) {
136 if (ipending & INT_MASK_FPU) {
  /src/sys/arch/pmax/pmax/
dec_5100.c 156 dec_5100_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
160 if (ipending & MIPS_INT_MASK_4) {
171 if (ipending & MIPS_INT_MASK_2) {
183 if (ipending & MIPS_INT_MASK_0) {
189 if (ipending & MIPS_INT_MASK_1) {
194 if (ipending & MIPS_INT_MASK_3) {
dec_3100.c 190 if (ipending & (cp0)) { \
197 dec_3100_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
201 if (ipending & MIPS_INT_MASK_3) {
217 if (ipending & MIPS_INT_MASK_4) {
dec_3min.c 317 dec_3min_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
325 if (ipending & MIPS_INT_MASK_4)
328 if (ipending & MIPS_INT_MASK_3) {
414 if ((ipending & MIPS_INT_MASK_0) && intrtab[SYS_DEV_OPT0].ih_func) {
419 if ((ipending & MIPS_INT_MASK_1) && intrtab[SYS_DEV_OPT1].ih_func) {
423 if ((ipending & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) {
dec_3maxplus.c 347 dec_3maxplus_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
351 if (ipending & MIPS_INT_MASK_4)
356 if (ipending & MIPS_INT_MASK_1) {
377 if ((ipending & MIPS_INT_MASK_1) && old_buscycle > (tick+49) * 25) {
384 if (ipending & MIPS_INT_MASK_0) {
387 if (ipending & MIPS_INT_MASK_3) {
dec_maxine.c 338 dec_maxine_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
340 if (ipending & MIPS_INT_MASK_4)
344 if (ipending & MIPS_INT_MASK_1) {
356 if (ipending & MIPS_INT_MASK_3) {
359 if (ipending & MIPS_INT_MASK_2) {
dec_3max.c 253 dec_3max_intr(uint32_t status, vaddr_t pc, uint32_t ipending)
259 if (ipending & MIPS_INT_MASK_1) {
282 if (ipending & MIPS_INT_MASK_0) {
302 if (ipending & MIPS_INT_MASK_3) {
  /src/sys/arch/ews4800mips/ews4800mips/
tr2_intr.c 150 uint32_t r, ipending; local in function:tr2_intr
153 while (ppl < (ipl = splintr(&ipending))) {
154 if (ipending & MIPS_INT_MASK_5) { /* CLOCK */
166 if (ipending & MIPS_INT_MASK_4) { /* KBD, MOUSE, SERIAL */
191 if (ipending & MIPS_INT_MASK_3) { /* VME */
204 if (ipending & MIPS_INT_MASK_2) { /* ETHER, SCSI */
226 (ipending & MIPS_INT_MASK_5)) {
239 if (ipending & MIPS_INT_MASK_1)
242 if (ipending & MIPS_INT_MASK_0) { /* FDD, PRINTER */
tr2a_intr.c 177 uint32_t r, intc_cause, ipending; local in function:tr2a_intr
182 while (ppl < (ipl = splintr(&ipending))) {
183 if ((ipending & MIPS_INT_MASK_5) && (intc_cause & INTC_INT5)) {
195 if ((ipending & MIPS_INT_MASK_4) && (intc_cause & INTC_INT4)) {
226 if ((ipending & MIPS_INT_MASK_3) && (intc_cause & INTC_INT3)) {
234 if ((ipending & MIPS_INT_MASK_2) && (intc_cause & INTC_INT2)) {
265 if ((ipending & MIPS_INT_MASK_1) && (intc_cause & INTC_INT1)) {
273 if ((ipending & MIPS_INT_MASK_0) && (intc_cause & INTC_INT0)) {
  /src/sys/arch/mips/atheros/
ar_intr.c 226 genath_iointr(int cpl, vaddr_t pc, uint32_t ipending)
230 /* move ipending to the most significant bits */
231 ipending *= __BIT(31) / (MIPS_INT_MASK_0 << (NINTRS-1));
232 while (ipending != 0) {
234 int index = __builtin_clz(ipending);
237 ipending <<= index;
238 KASSERT(ipending & __BIT(31));
245 ipending <<= 1;
  /src/sys/arch/playstation2/playstation2/
interrupt.c 125 uint32_t ipending; local in function:cpu_intr
139 while (ppl < (ipl = splintr(&ipending))) {
141 if (ipending & MIPS_INT_MASK_0) {
145 if (ipending & MIPS_INT_MASK_1) {
  /src/sys/arch/evbmips/ingenic/
intr.c 144 evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
151 snprintf(buffer, 256, "pending: %08x CR %08x\n", ipending,
164 if (ipending & MIPS_INT_MASK_1) {
212 if (ipending & MIPS_INT_MASK_2) {
218 if (ipending & MIPS_INT_MASK_0) {
  /src/sys/arch/evbmips/malta/
malta_intr.c 248 evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
252 if (ipending & (MIPS_INT_MASK_1 | MIPS_INT_MASK_3)) {
253 if (ipending & MIPS_INT_MASK_1)
255 if (ipending & MIPS_INT_MASK_3)
264 if (ipending & MIPS_INT_MASK_0) {
  /src/sys/arch/evbmips/mipssim/
mipssim_intr.c 107 evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
114 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
  /src/sys/arch/mips/ralink/
ralink_intr.c 350 evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
352 while (ipending != 0) {
353 const u_int bitno = 31 - __builtin_clz(ipending);
354 ipending ^= (1 << bitno);

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