| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXTargetMachine.h | 25 bool is64bit; member in class:llvm::NVPTXTargetMachine
39 CodeGenOpt::Level OP, bool is64bit);
46 bool is64Bit() const { return is64bit; }
|
| NVPTXTargetMachine.cpp | 98 static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) {
101 if (!is64Bit)
116 CodeGenOpt::Level OL, bool is64bit)
119 : LLVMTargetMachine(T, computeDataLayout(is64bit, UseShortPointersOpt), TT,
122 is64bit(is64bit), UseShortPointers(UseShortPointersOpt),
|
| /src/external/gpl3/gcc.old/dist/gcc/d/dmd/ |
| argtypes.c | 101 if (global.params.is64bit)
279 if (global.params.is64bit && !global.params.isLP64)
298 if (global.params.is64bit && !global.params.isLP64)
335 if (!global.params.is64bit)
344 if (!global.params.is64bit)
360 if (!global.params.is64bit)
367 if (global.params.is64bit && t->sym->fields.dim)
|
| target.h | 159 bool is64bit; // generate 64 bit code for x86_64; true by default for 64 bit dmd member in struct:Target
|
| target.d | 114 bool is64bit; // generate 64 bit code for x86_64; true by default for 64 bit dmd
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcTargetMachine.cpp | 30 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
36 if (!is64Bit)
44 if (is64Bit)
49 if (is64Bit)
73 bool Is64Bit, bool JIT) {
81 if (Is64Bit) {
93 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
94 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
97 CM, getEffectiveRelocModel(RM), is64bit, JIT),
100 Subtarget(TT, std::string(CPU), std::string(FS), *this, is64bit),
[all...] |
| SparcSubtarget.h | 39 bool Is64Bit;
62 const std::string &FS, const TargetMachine &TM, bool is64bit);
107 bool is64Bit() const { return Is64Bit; }
112 return is64Bit() ? 2047 : 0;
|
| SparcTargetMachine.h | 25 bool is64Bit;
31 CodeGenOpt::Level OL, bool JIT, bool is64bit);
|
| /src/sys/dev/pci/ |
| pci_map.c | 118 int s, is64bit, isrom; local
121 is64bit = (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT);
135 if (is64bit && (reg + 4) >= PCI_MAPREG_END)
162 if (is64bit) {
199 if ((is64bit && PCI_MAPREG_MEM64_SIZE(wmask) == 0) ||
200 (!is64bit && PCI_MAPREG_MEM_SIZE(mask) == 0)) {
|
| /src/external/apache2/llvm/dist/clang/lib/Frontend/ |
| InitHeaderSearch.cpp | 192 bool is64bit = arch == llvm::Triple::ppc64 || arch == llvm::Triple::x86_64; local
193 if (is64bit)
|
| /src/lib/libnvmm/ |
| libnvmm_x86.c | 1031 bool is64bit; member in struct:x86_decode_fsm
2060 if (__predict_true(fsm->is64bit)) {
2252 return (fsm->is64bit && /* RIP-relative only in 64bit mode */
2260 return (!fsm->is64bit && /* no disp32-only in 64bit mode */
2464 if (fsm->is64bit) {
2505 if (fsm->is64bit && (instr->operand_size == 4)) {
2548 if (fsm->is64bit && (instr->operand_size == 4)) {
2619 if (__predict_false(!fsm->is64bit)) {
2687 fsm.is64bit = is_64bit(state);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 417 bool is64bit = VT == MVT::f64; local
424 if (is64bit) {
444 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
1793 bool is64bit = VT == MVT::f64 || VT == MVT::i64; local
1797 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1800 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1803 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 3051 const bool Is64Bit = Subtarget.isPPC64();
3052 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
3053 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
3274 bool is64bit = Subtarget.isPPC64(); local
3295 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3316 if (is64bit) {
3343 if (is64bit) {
3369 if (is64bit) {
11189 bool is64bit = Subtarget.isPPC64();
11191 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO
12093 bool is64bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; local
12194 bool is64bit = Subtarget.isPPC64(); local
[all...] |
