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    Searched refs:isAligned (Results 1 - 25 of 25) sorted by relevancy

  /src/external/apache2/llvm/dist/clang/lib/Format/
WhitespaceManager.h 53 unsigned StartOfTokenColumn, bool isAligned = false,
113 bool IsAligned, bool ContinuesPPDirective, bool IsInsideToken);
129 bool IsAligned;
221 bool IsAligned);
  /src/external/apache2/llvm/dist/llvm/lib/Support/
OptimizedStructLayout.cpp 27 assert(isAligned(Field.Alignment, Field.Offset) &&
382 if (isAligned(FirstQueueToSearch->Alignment, LastEnd))
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
Loads.cpp 34 static bool isAligned(const Value *Base, const APInt &Offset, Align Alignment,
93 return isAligned(V, Offset, Alignment, DL);
185 return isAligned(V, Offset, Alignment, DL);
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
Alignment.h 138 inline bool isAligned(Align Lhs, uint64_t SizeInBytes) {
144 return isAligned(Lhs, reinterpret_cast<uintptr_t>(Addr));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSERegisterInfo.cpp 217 (!isIntN(OffsetBitSize, Offset) || !isAligned(OffsetAlign, Offset))) {
MipsConstantIslandPass.cpp 560 assert(isAligned(Alignment, Size) && "CP Entry not multiple of 4 bytes!");
MipsSEISelDAGToDAG.cpp 298 if (!isAligned(Alignment, CN->getZExtValue()))
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallFrameOptimization.cpp 225 if (!isAligned(StackAlign, CC.ExpectedDist))
X86InstrInfo.cpp 3815 bool isAligned =
3818 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3845 bool isAligned =
3848 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
6307 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6308 Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
6384 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6385 unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
6451 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6452 Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget)
    [all...]
X86FrameLowering.cpp 2260 assert(isAligned(MFI.getObjectAlign(FI), -(Offset + StackSize)));
2268 assert(isAligned(MFI.getObjectAlign(FI), -(Offset + StackSize)));
X86ISelLowering.cpp 2296 (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
Assembler.cpp 319 assert(isAligned(kFunctionAlignment, FunctionAddress) &&
  /src/external/apache2/llvm/dist/llvm/lib/IR/
DataLayout.cpp 59 if (!isAligned(TyAlign, StructSize)) {
74 if (!isAligned(StructAlignment, StructSize)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 3384 if (!isAligned(A, AM.BaseOffs))
3489 if (Op.size() >= 8 && Op.isAligned(Align(8)))
3491 if (Op.size() >= 4 && Op.isAligned(Align(4)))
3493 if (Op.size() >= 2 && Op.isAligned(Align(2)))
HexagonISelDAGToDAG.cpp 1356 if (!isAligned(Alignment, V))
1377 !isAligned(Alignment, cast<BlockAddressSDNode>(N)->getOffset()))
1402 if (!isAligned(Alignment, Const->getZExtValue()))
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 179 return isMemset() || llvm::isAligned(AlignCheck, SrcAlign.value());
182 return DstAlignCanChange || llvm::isAligned(AlignCheck, DstAlign.value());
184 bool isAligned(Align AlignCheck) const {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 1177 assert(isAligned(ST.getStackAlignment(), FPDiff) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCRegisterInfo.cpp 574 assert(isAligned(MaxAlign, maxCallFrameSize) &&
PPCISelLowering.cpp 2593 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2603 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2687 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2711 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2738 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2749 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
16064 (Op.isAligned(Align(16)) ||
17276 if (!Align || isAligned(*Align, Imm)) {
17307 if (isIntS16Immediate(CN, Imm) && (!Align || isAligned(*Align, Imm))) {
17315 (!Align || isAligned(*Align, CNImm)))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
DeadStoreElimination.cpp 615 assert(isAligned(PrefAlign, ToRemoveSize) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMConstantIslandPass.cpp 549 assert(isAligned(Alignment, Size) && "CP Entry not multiple of 4 bytes!");
ARMISelLowering.cpp 17217 (Op.isAligned(Align(16)) ||
17223 (Op.isAligned(Align(8)) ||
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Coroutines/
CoroFrame.cpp 720 if (!isAligned(F.TyAlignment, LayoutField.Offset))
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 15711 isAligned(*Alignment, LD->getSrcValueOffset())) {
17833 isAligned(*Alignment, ST->getSrcValueOffset())) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 11628 if (Op.isAligned(AlignCheck))
11659 if (Op.isAligned(AlignCheck))

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