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    Searched refs:isAssignedRegDep (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonHazardRecognizer.cpp 144 if (S.isAssignedRegDep() && S.getLatency() == 0 &&
159 if (S.isAssignedRegDep() && S.getLatency() == 0 &&
HexagonSubtarget.cpp 492 if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
540 if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
556 if (I.isAssignedRegDep() && I.getLatency() == 0 &&
HexagonMachineScheduler.cpp 707 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() &&
716 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() &&
HexagonVLIWPacketizer.cpp 1929 if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) ||
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGVLIW.cpp 140 assert(!Succ.isAssignedRegDep() &&
ScheduleDAGRRList.cpp 558 if (Pred.isAssignedRegDep()) {
772 if (Succ.isAssignedRegDep() && LiveRegDefs[Succ.getReg()] == SU) {
841 if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){
887 if (Succ.isAssignedRegDep()) {
901 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg &&
1356 if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU)
2853 if (!SuccPred.isAssignedRegDep())
3034 assert(!Edge.isAssignedRegDep());
ScheduleDAGFast.cpp 164 if (Pred.isAssignedRegDep()) {
193 if (Succ.isAssignedRegDep()) {
475 if (Pred.isAssignedRegDep()) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ScheduleDAG.cpp 86 if (TRI && isAssignedRegDep())
710 if (PredDep.isAssignedRegDep() &&
MachinePipeliner.cpp 2727 if (SI.isAssignedRegDep())
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleDAG.h 211 bool isAssignedRegDep() const {

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