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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleDAG.h 278 bool isCommutable : 1; ///< Is a commutable instruction.
310 isCallOp(false), isTwoAddress(false), isCommutable(false),
321 isCallOp(false), isTwoAddress(false), isCommutable(false),
331 isCommutable(false), hasPhysRegUses(false), hasPhysRegDefs(false),
MachineInstr.h 1046 bool isCommutable(QueryType Type = IgnoreBundle) const {
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCInstrDesc.h 472 bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 98 SU->isCommutable = Old->isCommutable;
459 if (MCID.isCommutable())
460 SU->isCommutable = true;
ScheduleDAGFast.cpp 261 if (MCID.isCommutable())
262 NewSU->isCommutable = true;
ScheduleDAGRRList.cpp 1041 if (MCID.isCommutable())
1042 NewSU->isCommutable = true;
3118 (!SU.isCommutable && SuccSU->isCommutable)) &&
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenInstruction.h 258 bool isCommutable : 1;
InstrDocsEmitter.cpp 120 FLAG(isCommutable)
CodeGenInstruction.cpp 388 isCommutable = R->getValueAsBit("isCommutable");
InstrInfoEmitter.cpp 966 if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)";
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNDPPCombine.cpp 542 if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1]
565 assert(Use == Src1 && OrigMI.isCommutable()); // by check [1]
SIOptimizeExecMasking.cpp 436 if (!SaveExecInst->isCommutable())
SIShrinkInstructions.cpp 104 if (TryToCommute && MI.isCommutable()) {
724 if (!MI.isCommutable() || !TII->commuteInstruction(MI) ||
SIFoldOperands.cpp 1093 if (!MI->isCommutable())
AMDGPUISelDAGToDAG.cpp 2959 if (Desc.isCommutable()) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.cpp 96 if (Use.isCommutable())
102 Use.isCommutable()) {
SystemZShortenInst.cpp 360 (!MI.isCommutable() ||
SystemZInstrInfo.cpp 1251 : ((OpNum == 1 && MI.isCommutable())
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ScheduleDAGInstrs.cpp 582 SU->isCommutable = MI.isCommutable();
TargetInstrInfo.cpp 258 assert(MI.isCommutable() &&
303 if (!MCID.isCommutable())
MachineCSE.cpp 541 if (!FoundCSE && MI->isCommutable()) {
TwoAddressInstructionPass.cpp 1064 if (!MI->isCommutable())
RegisterCoalescer.cpp 830 if (!DefMI->isCommutable())
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsInstrInfo.cpp 688 if (!MCID.isCommutable())
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVInstrInfo.cpp 1157 if (!Desc.isCommutable())

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