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    Searched refs:isOperationExpand (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
BasicTTIImpl.h 773 if (!TLI->isOperationExpand(ISD, LT.second)) {
930 if (!TLI->isOperationExpand(ISD, DstLT.second))
953 if (!TLI->isOperationExpand(ISD, DstLT.second))
1041 !TLI->isOperationExpand(ISD, LT.second)) {
1867 } else if (!TLI->isOperationExpand(ISD, LT.second)) {
TargetLowering.h 1207 bool isOperationExpand(unsigned Op, EVT VT) const {
2786 return MathUsed && (VT.isSimple() || !isOperationExpand(Opcode, VT));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUTargetTransformInfo.cpp 547 if (!TLI->isOperationExpand(ISD, LT.second)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCTargetTransformInfo.cpp 957 if (TLI->isOperationExpand(ISD, LT1.second))
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeDAG.cpp 3644 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
DAGCombiner.cpp 14342 (!DAG.getTargetLoweringInfo().isOperationExpand(ISD::FPOW, VT) &&
14343 DAG.getTargetLoweringInfo().isOperationExpand(ISD::FCBRT, VT)))
18658 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) {
LegalizeVectorTypes.cpp 3129 TLI.isOperationExpand(N->getOpcode(), VT.getScalarType())) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 2001 if (isOperationExpand(Op, MVT::f32))
5367 return VT.isSimple() || !isOperationExpand(Opcode, VT);
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