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  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCInstrDesc.h 107 /// operand that controls an isPredicable() instruction.
329 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
622 if (isPredicable()) {
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenInstruction.h 152 bool isPredicable;
256 bool isPredicable : 1;
CodeGenInstruction.cpp 28 isPredicable = false;
109 isPredicable = true;
385 isPredicable = !R->getValueAsBit("isUnpredicable") && (
386 Operands.isPredicable || R->getValueAsBit("isPredicable"));
InstrDocsEmitter.cpp 118 FLAG(isPredicable)
InstrInfoEmitter.cpp 964 if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)";
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 806 if (!NewMCID.isPredicable())
810 SkipPred = !NewMCID.isPredicable();
899 if (!NewMCID.isPredicable())
903 SkipPred = !NewMCID.isPredicable();
968 if (!MCID.isPredicable() && NewMCID.isPredicable())
ThumbRegisterInfo.cpp 561 if (MI.isPredicable())
ARMConstantIslandPass.cpp 623 MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1));
2185 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1);
2379 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1);
ARMBaseInstrInfo.h 181 bool isPredicable(const MachineInstr &MI) const override;
ARMBaseInstrInfo.cpp 693 /// isPredicable - Return true if the specified instruction can be predicated.
696 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
697 if (!MI.isPredicable())
2282 if (!isPredicable(*MI))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonExpandCondsets.cpp 221 bool isPredicable(MachineInstr *MI);
723 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) {
724 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
961 if (!DefI || !isPredicable(DefI))
1228 if (!RDef || !HII->isPredicable(*RDef)) {
1239 if (!RDef || !HII->isPredicable(*RDef)) {
HexagonEarlyIfConv.cpp 482 if (!HII->isPredicable(*Def1) || !HII->isPredicable(*Def3))
662 // HexagonInstrInfo::isPredicable will consider these stores are non-
680 // TargetInstrInfo::isPredicable takes a non-const pointer.
681 return MI->mayStore() && HII->isPredicable(const_cast<MachineInstr&>(*MI));
HexagonInstrInfo.h 247 bool isPredicable(const MachineInstr &MI) const override;
HexagonInstrInfo.cpp 1593 assert (isPredicable(MI) && "Expected predicable instruction");
1670 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
1671 if (!MI.getDesc().isPredicable())
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600InstrInfo.h 182 bool isPredicable(const MachineInstr &MI) const override;
R600InstrInfo.cpp 854 bool R600InstrInfo::isPredicable(const MachineInstr &MI) const {
872 return TargetInstrInfo::isPredicable(MI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.h 247 bool isPredicable(const MachineInstr &MI) const override;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetInstrInfo.h 1471 virtual bool isPredicable(const MachineInstr &MI) const {
1472 return MI.getDesc().isPredicable();
MachineInstr.h 874 bool isPredicable(QueryType Type = AllInBundle) const {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ImplicitNullChecks.cpp 374 if (!MI.mayLoadOrStore() || MI.isPredicable())
TargetInstrInfo.cpp 326 if (!MI.isPredicable())
339 if (!MI.isPredicable())
EarlyIfConversion.cpp 328 if (!TII->isPredicable(*I) || TII->isPredicated(*I)) {
MachineSink.cpp 1016 if (!(MI.mayLoad() && !MI.isPredicable()))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiInstrInfo.cpp 467 if (!MI->isPredicable())
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 6982 bool isPredicable =
6984 size_t NumPredOps = isPredicable ? 1 : 0;
7613 if (!MCID.isPredicable())
7629 } else if (isThumbTwo() && MCID.isPredicable() &&
7635 } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
7639 } else if (!MCID.isPredicable()) {
10849 if (MCID.isPredicable()) {
10873 if (MCID.isPredicable()) {
10900 if (MCID.isPredicable()) {

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