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    Searched refs:isPredicated (Results 1 - 25 of 42) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCTargetDesc.h 46 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
ARMMCTargetDesc.cpp 181 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCInstrInfo.cpp 181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
213 CantAnalyze = !isPredicated(*I);
221 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonVLIWPacketizer.cpp 368 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
570 if (!HII->isPredicated(MI))
701 if (HII->isPredicated(PacketMI)) {
702 if (!HII->isPredicated(MI))
926 if (!HII->isPredicated(*I))
953 assert(QII->isPredicated(MI) && "Must be predicated instruction");
1207 if (HII->isPredicated(I) || HII->isPredicated(J))
1247 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1468 if (HII->isPredicated(I) && HII->isPredicated(J) &
    [all...]
HexagonExpandCondsets.cpp 344 if (HII->isPredicated(*DefI))
422 if (HII->isPredicated(*DefI))
492 if (!HII->isPredicated(*DefI))
724 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
759 if (PredValid && HII->isPredicated(*MI)) {
917 if (!HII->isPredicated(*MI))
990 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
HexagonInstrInfo.h 223 bool isPredicated(const MachineInstr &MI) const override;
388 bool isPredicated(unsigned Opcode) const;
HexagonPeephole.cpp 235 if (QII->isPredicated(MI)) {
HexagonInstrInfo.cpp 611 if (Term != MBB.end() && isPredicated(*Term) &&
1580 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
2163 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2447 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2470 assert(isPredicated(MI));
2476 assert(isPredicated(Opcode));
2494 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
3177 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3242 if (isPredicated(MI)) {
3767 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old for
    [all...]
HexagonNewValueJump.cpp 124 if (QII->isPredicated(*II))
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CriticalAntiDepBreaker.cpp 178 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI);
253 if (!TII->isPredicated(MI)) {
608 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI))
IfConversion.cpp 1110 bool isPredicated = TII->isPredicated(MI);
1122 if (!isPredicated) {
1137 if (BBI.ClobbersPred && !isPredicated) {
1992 bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T);
1993 bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T);
2084 if (TI != BBI.BB->end() && TII->isPredicated(*TI))
2142 if (I.isDebugInstr() || TII->isPredicated(I))
2202 if (!TII->isPredicated(I) && !MI->isDebugInstr()) {
2256 if (FromTI != FromMBB.end() && !TII->isPredicated(*FromTI)
    [all...]
TargetSchedule.cpp 306 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
AggressiveAntiDepBreaker.cpp 381 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) ||
459 TII->isPredicated(MI) || MI.isInlineAsm();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCInstrInfo.h 275 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
327 bool isPredicated() const;
HexagonMCChecker.cpp 68 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) {
435 if (std::get<2>(Producer).isPredicated() &&
436 (!Consumer.isPredicated() ||
HexagonMCInstrInfo.cpp 35 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const {
718 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
927 if (!isPredicated(MCII, MCI))
HexagonMCCodeEmitter.cpp 759 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) {
763 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600InstrInfo.h 180 bool isPredicated(const MachineInstr &MI) const override;
R600Packetizer.cpp 79 if (TII->isPredicated(*BI))
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLowOverheadLoops.cpp 866 bool isPredicated = isVectorPredicated(&MI);
870 return isPredicated;
894 if (MO.isUse() && isPredicated)
938 bool isPredicated = isVectorPredicated(&MI);
942 if (isPredicated)
948 else if (!isPredicated && retainsOrReduces)
950 else if (!isPredicated)
ARMBaseInstrInfo.cpp 361 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
404 if (!isPredicated(*I) &&
433 if (AllowModify && !isPredicated(MBB.back()) &&
532 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
2988 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
2997 isPredicated(*PotentialAND))
3116 if (isPredicated(*MI))
3245 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
3263 if (isPredicated(MI))
4931 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)
    [all...]
ARMSLSHardening.cpp 119 assert(!TII->isPredicated(MI));
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
VectorUtils.cpp 1062 (!isPredicated(B->getParent()) || EnablePredicatedInterleavedMemAccesses)) {
1164 if ((isPredicated(BlockA) || isPredicated(BlockB)) &&
  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
VectorUtils.h 871 bool isPredicated(BasicBlock *BB) const {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.h 504 bool isPredicated(const MachineInstr &MI) const override;

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