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    Searched refs:isRegLoc (Results 1 - 25 of 30) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CallingConvLower.cpp 76 if (ValAssign.isRegLoc()) {
228 HaveRegParm = Locs.back().isRegLoc();
234 if (Locs[I].isRegLoc())
288 Loc1.isRegLoc() != Loc2.isRegLoc() ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallLowering.cpp 113 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
154 assert(VA.isRegLoc() && "Value should be in reg");
155 assert(NextVA.isRegLoc() && "Value should be in reg");
284 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
325 assert(VA.isRegLoc() && "Value should be in reg");
326 assert(NextVA.isRegLoc() && "Value should be in reg");
ARMFastISel.cpp 1895 if (VA.isRegLoc() && !VA.needsCustom()) {
1901 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1975 if (VA.isRegLoc() && !VA.needsCustom()) {
1987 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2117 if (!VA.isRegLoc())
ARMISelLowering.cpp 2208 if (NextVA.isRegLoc())
2375 if (VA.isRegLoc()) {
2387 } else if (VA.isRegLoc()) {
2881 if (!VA.isRegLoc())
2883 if (!ArgLocs[++i].isRegLoc())
2886 if (!ArgLocs[++i].isRegLoc())
2888 if (!ArgLocs[++i].isRegLoc())
2891 } else if (!VA.isRegLoc()) {
2991 assert(VA.isRegLoc() && "Can only return in registers!");
4317 if (VA.isRegLoc()) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCISelLowering.cpp 284 if (VA.isRegLoc()) {
377 if (VA.isRegLoc()) {
482 if (VA.isRegLoc()) {
634 if (VA.isRegLoc())
662 if (!VA.isRegLoc())
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
CallingConvLower.h 145 bool isRegLoc() const { return !isMem; }
150 Register getLocReg() const { assert(isRegLoc()); return Loc; }
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CallLowering.cpp 920 if (!ArgLoc.isRegLoc())
999 if (Loc1.isRegLoc() != Loc2.isRegLoc())
1002 if (Loc1.isRegLoc()) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 320 if (VA.isRegLoc()) {
441 if (VA.isRegLoc())
528 assert(VA.isRegLoc() && "Can only return in registers!");
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 1068 if (VA.isRegLoc()) {
1162 if (VA.isRegLoc()) {
1299 if (VA.isRegLoc()) {
1470 if (VA.isRegLoc())
1498 if (!VA.isRegLoc())
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 233 assert(VA.isRegLoc() && "Can only return in registers!");
316 assert(VA.isRegLoc() && "Can only return in registers!");
414 if (VA.isRegLoc()) {
593 if (VA.isRegLoc()) {
866 if (VA.isRegLoc()) {
870 if (NextVA.isRegLoc()) {
900 if (VA.isRegLoc()) {
1052 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1164 if (VA.isRegLoc()) {
1199 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 626 if (VA.isRegLoc()) {
671 if (VA.isRegLoc())
892 if (VA.isRegLoc()) {
1032 assert(VA.isRegLoc() && "Can only return in registers!");
1207 if (!ArgLocs[i].isRegLoc())
1250 if (!VA.isRegLoc()) {
1274 if (!VA.isRegLoc())
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 458 if (VA.isRegLoc()) {
555 assert(VA.isRegLoc() && "Can only return in registers!");
685 if (VA.isRegLoc()) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 640 if (VA.isRegLoc()) {
762 assert(VA.isRegLoc() && "Can only return in registers!");
848 if (VA.isRegLoc()) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 1397 !VA.isRegLoc() || VA.needsCustom())
1505 assert(VA.isRegLoc() && "Can only return in registers!");
1745 assert(VA.isRegLoc() && "Can only return in registers!");
PPCISelLowering.cpp 4002 if (VA.isRegLoc()) {
5092 assert(VA.isRegLoc() && "Can only return in registers!");
5807 if (VA.isRegLoc()) {
6922 assert(I != End && ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom() &&
6942 if (I != End && ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom()) {
6952 if (VA.isRegLoc()) {
6975 assert(VA.isRegLoc() && "MemLocs should already be handled.");
7017 for (; Offset != StackSize && ArgLocs[I].isRegLoc();
7039 if (VA.isRegLoc() && !VA.needsCustom()) {
7198 while (LoadOffset + PtrByteSize <= ByValSize && ArgLocs[I].isRegLoc()) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsCallLowering.cpp 29 if (VA.isRegLoc()) {
MipsFastISel.cpp 1229 if (VA.isRegLoc() && !VA.needsCustom()) {
1720 if (!VA.isRegLoc())
MipsISelLowering.cpp 3282 if (VA.isRegLoc()) {
3335 if (VA.isRegLoc()) {
3496 assert(VA.isRegLoc() && "Can only return in registers!");
3645 bool IsRegLoc = VA.isRegLoc();
3663 if (IsRegLoc) {
3693 } else { // VA.isRegLoc()
3813 assert(VA.isRegLoc() && "Can only return in registers!");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 1148 if (VA.isRegLoc()) {
1465 assert(VA.isRegLoc() && "Can only return in registers!");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64CallLowering.cpp 733 if (ArgLoc.isRegLoc())
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 339 assert(VA.isRegLoc() && "Can only return in registers!");
416 if (VA.isRegLoc()) {
674 if (VA.isRegLoc()) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 518 if (VA.isRegLoc())
834 if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8)
837 bool InReg = VA.isRegLoc() &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FastISel.cpp 1235 if (!VA.isRegLoc())
3387 if (VA.isRegLoc()) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 7072 assert(VA.isRegLoc() && "Expected register VA assignment");
7265 else if (VA.isRegLoc())
7519 if (IsF64OnRV32DSoftABI && VA.isRegLoc()) {
7600 if (VA.isRegLoc()) {
7788 assert(VA.isRegLoc() && "Can only return in registers!");
7792 assert(VA.isRegLoc() && "Expected return via registers");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 3043 if (VA.isRegLoc() && !VA.needsCustom()) {
3794 if (!VA.isRegLoc())

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