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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
LiveRegUnits.h 52 if (O->isRegMask())
169 return MOP.isRegMask() || (MOP.isReg() && !MOP.isDebug() &&
MachineOperand.h 344 /// isRegMask - Tests if this is a MO_RegisterMask operand.
345 bool isRegMask() const { return OpKind == MO_RegisterMask; }
631 assert(isRegMask() && "Wrong MachineOperand accessor");
699 assert(isRegMask() && "Wrong MachineOperand mutator");
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
LiveRegUnits.cpp 43 if (MOP.isRegMask()) {
63 if (MOP.isRegMask()) {
LivePhysRegs.cpp 47 if (MOP.isRegMask()) {
98 } else if (O->isRegMask())
108 if (Reg.second->isRegMask() &&
RegUsageInfoPropagate.cpp 71 if (MO.isRegMask())
DeadMachineInstructionElim.cpp 171 } else if (MO.isRegMask()) {
CriticalAntiDepBreaker.cpp 259 if (MO.isRegMask()) {
369 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
MachineInstrBundle.cpp 317 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
MachineCopyPropagation.cpp 213 if (MO.isRegMask())
239 if (MO.isRegMask())
669 if (MO.isRegMask())
ShrinkWrap.cpp 293 } else if (MO.isRegMask()) {
MachineCSE.cpp 236 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
378 if (MO.isRegMask())
RegisterScavenging.cpp 121 if (MO.isRegMask()) {
309 if (MO.isRegMask())
ImplicitNullChecks.cpp 242 auto IsRegMask = [](const MachineOperand &MO) { return MO.isRegMask(); };
243 (void)IsRegMask;
245 assert(!llvm::any_of(MI->operands(), IsRegMask) &&
MachineInstr.cpp 241 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
1048 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1493 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
2048 if (MO.isRegMask()) {
RDFRegisters.cpp 80 if (Op.isRegMask())
VirtRegMap.cpp 538 if (MO.isRegMask())
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86VZeroUpper.cpp 160 if (MI.isCall() && MO.isRegMask() && !clobbersAllYmmAndZmmRegs(MO))
176 if (MO.isRegMask())
X86PreTileConfig.cpp 103 MI.operands(), [](MachineOperand &MO) { return MO.isRegMask(); });
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCCTRLoops.cpp 89 } else if (MO.isRegMask()) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
RDFDeadCode.cpp 69 if (Op.isRegMask()) {
HexagonVLIWPacketizer.cpp 797 if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))
840 if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg))
1277 if (!OpJ.isRegMask())
1284 } else if (OpI.isRegMask()) {
1600 } else if (!Op.isRegMask()) {
HexagonBlockRanges.cpp 351 if (!Op.isRegMask())
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp 561 } else if (U.isRegMask()) {
697 } else if (MO.isRegMask()) {
AArch64CollectLOH.cpp 502 if (MO.isRegMask()) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/
DbgEntityHistoryCalculator.cpp 513 } else if (MO.isRegMask()) {

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