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    Searched refs:isUInt (Results 1 - 25 of 95) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
X86AsmParserCommon.h 18 (isUInt<16>(Value) && isInt<8>(static_cast<int16_t>(Value)));
23 (isUInt<32>(Value) && isInt<8>(static_cast<int32_t>(Value)));
35 return isUInt<8>(Value) || isInt<8>(Value);
39 return isUInt<4>(Value);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/
SystemZMCCodeEmitter.cpp 188 assert(isUInt<4>(Base) && isUInt<12>(Disp));
198 assert(isUInt<4>(Base) && isInt<20>(Disp));
209 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
220 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
232 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len))
    [all...]
SystemZInstPrinter.cpp 80 assert(isUInt<N>(Value) && "Invalid uimm argument");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CompressJumpTables.cpp 145 if (isUInt<8>(Span / 4)) {
151 if (isUInt<16>(Span / 4)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCFrameLowering.cpp 65 if (isUInt<6>(AbsAmount))
138 if (isUInt<6>(VarArgsBytes))
187 TII->get(isUInt<6>(MFI.getStackSize()) ? ARC::ADD_rru6
255 if (isUInt<6>(StackSize))
283 if (isUInt<6>(MoveAmount))
298 if (isUInt<6>(4 * StackSlotsUsedByFunclet))
325 if (isUInt<6>(VarArgsBytes))
455 if (isUInt<6>(NumBytes))
ARCExpandPseudos.cpp 64 isUInt<6>(SI.getOperand(2).getImm()) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
ARCRegisterInfo.cpp 74 unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
115 TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm))
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/
PPCAsmParser.cpp 316 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
317 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
318 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
319 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
320 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
322 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
324 isUInt<6>(getImm()) &&
326 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
328 isUInt<7>(getImm()) &&
330 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm());
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/ADT/
PointerEmbeddedInt.h 64 assert((std::is_signed<IntT>::value ? isInt<Bits>(I) : isUInt<Bits>(I)) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRRegisterInfo.cpp 186 if (isUInt<6>(Offset)) {
248 assert(isUInt<6>(Offset) && "Offset is out of range");
AVRFrameLowering.cpp 119 unsigned Opcode = (isUInt<6>(FrameSize)) ? AVR::SBIWRdK : AVR::SUBIWRdK;
195 if (isUInt<6>(FrameSize)) {
379 if (isUInt<6>(Amount)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZTargetTransformInfo.cpp 54 if (isUInt<32>(Imm.getZExtValue()))
107 if (isUInt<32>(Imm.getZExtValue()))
115 if (isUInt<32>(Imm.getZExtValue()))
118 if (isUInt<32>(-Imm.getSExtValue()))
133 if (isUInt<32>(Imm.getZExtValue()))
146 if (isUInt<32>(~Imm.getZExtValue()))
210 if (isUInt<32>(Imm.getZExtValue()))
212 if (isUInt<32>(-Imm.getSExtValue()))
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/
RISCVDisassembler.cpp 272 assert(isUInt<N>(Imm) && "Invalid immediate");
290 assert(isUInt<N>(Imm) && "Invalid immediate");
310 assert(isUInt<N>(Imm) && "Invalid immediate");
321 assert(isUInt<6>(Imm) && "Invalid immediate");
332 assert(isUInt<3>(Imm) && "Invalid immediate");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUBaseInfo.cpp 1025 return 0 <= Id && isUInt<ID_WIDTH_>(Id);
1029 return 0 <= Offset && isUInt<OFFSET_WIDTH_>(Offset);
1033 return 0 <= (Width - 1) && isUInt<WIDTH_M1_WIDTH_>(Width - 1);
1246 return 0 <= MsgId && isUInt<ID_WIDTH_>(MsgId);
1272 return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
1297 return 0 <= StreamId && isUInt<STREAM_ID_WIDTH_>(StreamId);
1751 if (isInt<16>(Literal) || isUInt<16>(Literal)) {
1765 if (isInt<16>(Literal) || isUInt<16>(Literal))
1778 if (isInt<16>(Literal) || isUInt<16>(Literal))
1824 return hasSMEMByteOffset(ST) ? isUInt<20>(EncodedOffset
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
MathExtras.h 392 /// to keep MSVC from (incorrectly) warning on isUInt<64> that we're shifting
395 constexpr inline std::enable_if_t<(N < 64), bool> isUInt(uint64_t X) {
396 static_assert(N > 0, "isUInt<0> doesn't make sense");
400 constexpr inline std::enable_if_t<N >= 64, bool> isUInt(uint64_t) {
405 template <> constexpr inline bool isUInt<8>(uint64_t x) {
408 template <> constexpr inline bool isUInt<16>(uint64_t x) {
411 template <> constexpr inline bool isUInt<32>(uint64_t x) {
424 return isUInt<N + S>(x) && (x % (UINT64_C(1) << S) == 0);
  /src/external/apache2/llvm/dist/llvm/lib/IR/
DataLayout.cpp 251 if (!isUInt<24>(AddrSpace))
309 if (!isUInt<24>(AddrSpace))
403 if (!isUInt<16>(ABIAlign))
417 if (!isUInt<16>(PrefAlign))
566 if (!isUInt<24>(bit_width))
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/
RISCVAsmParser.cpp 469 (isRV64() || (isInt<32>(Imm) || isUInt<32>(Imm)));
480 return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
493 return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
504 return (isRV64() && isUInt<5>(Imm)) || isUInt<4>(Imm);
513 return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
551 (isUInt<5>(Imm) || (Imm >= 0xfffe0 && Imm <= 0xfffff)) &&
650 return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None |
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/
SystemZDisassembler.cpp 172 if (!isUInt<N>(Imm))
180 if (!isUInt<N>(Imm))
251 assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/Disassembler/
PPCDisassembler.cpp 196 assert(isUInt<N>(Imm) && "Invalid immediate");
204 assert(isUInt<N>(Imm) && "Invalid immediate");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 333 bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); }
334 bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }
335 bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }
344 bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); }
2492 if (!isUInt<32>(RegLo)) {
2497 if (!isUInt<32>(RegHi)) {
4539 if (!isUInt<ENTRY##_WIDTH>(VALUE)) \
4544 if (!isUInt<sizeof(KD.group_segment_fixed_size) * CHAR_BIT>(Val))
4548 if (!isUInt<sizeof(KD.private_segment_fixed_size) * CHAR_BIT>(Val))
4552 if (!isUInt<sizeof(KD.kernarg_size) * CHAR_BIT>(Val)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kCollapseMOVEMPass.cpp 134 assert(isUInt<16>(Value) && "Mask must fit 16 bit");
  /src/external/apache2/llvm/dist/llvm/tools/llvm-cvtres/
llvm-cvtres.cpp 96 if (Now < 0 || !isUInt<32>(Now))
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/
VEAsmParser.cpp 257 return isUInt<1>(Value);
268 return isUInt<2>(Value);
279 return isUInt<3>(Value);
290 return isUInt<4>(Value);
301 return isUInt<6>(Value);
312 return isUInt<7>(Value);
334 return isUInt<6>(Value);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 797 isUInt<8>(EltOffset0 / 64) && isUInt<8>(EltOffset1 / 64)) {
807 if (isUInt<8>(EltOffset0) && isUInt<8>(EltOffset1)) {
837 if (isUInt<8>(Max - Min)) {
1073 assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) &&
1171 assert((isUInt<8>(NewOffset0) && isUInt<8>(NewOffset1)) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVInstrInfo.cpp 864 Ok = isUInt<4>(Imm);
867 Ok = isUInt<5>(Imm);
870 Ok = isUInt<12>(Imm);
876 Ok = isUInt<20>(Imm);
880 Ok = isUInt<6>(Imm);
882 Ok = isUInt<5>(Imm);

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