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    Searched refs:isVectorLoadExtDesirable (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.h 73 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
WebAssemblyISelLowering.cpp 679 bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.h 1048 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
AArch64ISelLowering.cpp 4082 bool AArch64TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.h 448 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
ARMISelLowering.cpp 17441 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.h 1225 bool isVectorLoadExtDesirable(SDValue) const override;
X86ISelLowering.cpp     [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 2677 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 5809 TLI.isVectorLoadExtDesirable(SDValue(SDValue(GN0, 0)))) {
10441 // This combine is controlled by TargetLowering::isVectorLoadExtDesirable.
10451 !TLI.isVectorLoadExtDesirable(SDValue(N, 0)))
10687 DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
10725 if (!TLI.isVectorLoadExtDesirable(SDValue(N, 0)))
11958 TLI.isVectorLoadExtDesirable(SDValue(SDValue(GN0, 0)))) {

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