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    Searched refs:isWave32 (Results 1 - 22 of 22) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.h 33 bool isWave32;
279 return isWave32 ? &AMDGPU::SReg_32RegClass
284 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
SILateBranchLowering.cpp 124 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
125 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
SIOptimizeExecMasking.cpp 64 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC))
80 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) &&
302 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
AMDGPUAtomicOptimizer.cpp 311 if (ST->isWave32())
366 if (!ST->isWave32()) {
411 if (!ST->isWave32()) {
504 if (ST->isWave32()) {
SIRegisterInfo.cpp 105 bool IsWave32;
111 bool IsWave32, MachineBasicBlock::iterator MI, int Index,
117 IsWave32(IsWave32) {
122 if (IsWave32) {
139 Data.PerVGPR = IsWave32 ? 32 : 64;
183 IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass;
275 SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) {
492 if (isWave32) {
    [all...]
SIFrameLowering.cpp 559 if (ST.isWave32()) {
709 ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64;
786 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
787 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
1089 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
1090 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
SIInstrInfo.cpp 1071 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1085 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1128 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1131 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1146 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1149 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1757 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
1758 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
1769 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
1770 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC
    [all...]
GCNSubtarget.h 1090 bool isWave32() const {
SIAnnotateControlFlow.cpp 127 IntMask = ST.isWave32() ? Type::getInt32Ty(Context)
SIOptimizeExecMaskingPreRA.cpp 314 const bool Wave32 = ST.isWave32();
SIPreEmitPeephole.cpp 80 const bool IsWave32 = ST.isWave32();
82 const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
83 const unsigned And = IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
84 const unsigned AndN2 = IsWave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64;
85 const unsigned Mov = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
SILowerControlFlow.cpp 637 bool IsWave32 = ST.isWave32();
642 TII->get(IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64), Exec)
687 TII->get(IsWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64), Exec)
695 TII->get(IsWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
782 if (ST.isWave32()) {
SILowerI1Copies.cpp 47 bool IsWave32 = false;
420 return MRI.createVirtualRegister(ST.isWave32() ? &AMDGPU::SReg_32RegClass
456 IsWave32 = ST->isWave32();
458 if (IsWave32) {
565 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
686 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
SIWholeQuadMode.cpp 873 Register VCC = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC;
976 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
1522 if (ST->isWave32()) {
AMDGPUAsmPrinter.cpp 415 if (MF.getSubtarget<GCNSubtarget>().isWave32()) {
1357 if (STM.isWave32())
SIShrinkInstructions.cpp 601 unsigned VCCReg = ST.isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC;
AMDGPURegisterBankInfo.cpp 721 const unsigned WaveAndOpc = Subtarget.isWave32() ?
723 const unsigned MovTermOpc = Subtarget.isWave32() ?
725 const unsigned XorTermOpc = Subtarget.isWave32() ?
727 const unsigned AndSaveExecOpc = Subtarget.isWave32() ?
729 const unsigned ExecReg = Subtarget.isWave32() ?
SIInstrInfo.h 1051 bool isWave32() const;
SIInsertWaitcnts.cpp 1562 TII->get(ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64),
AMDGPUISelDAGToDAG.cpp 2292 Cond = SDValue(CurDAG->getMachineNode(ST->isWave32() ? AMDGPU::S_AND_B32
2295 CurDAG->getRegister(ST->isWave32() ? AMDGPU::EXEC_LO
SIISelLowering.cpp 3533 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
3562 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3564 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
3599 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3600 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
11790 if (ST.isWave32() && !MF.empty()) {
AMDGPUInstructionSelector.cpp 2119 Opcode = STI.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;

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