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    Searched refs:ixCG_CLKPIN_CNTL_2 (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ci_baco.c 115 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
amdgpu_fiji_baco.c 98 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
amdgpu_polaris_baco.c 110 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
amdgpu_tonga_baco.c 106 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_d.h 59 #define ixCG_CLKPIN_CNTL_2 0xc05001a4
smu_7_0_1_d.h 60 #define ixCG_CLKPIN_CNTL_2 0xc05001a4
smu_7_1_0_d.h 59 #define ixCG_CLKPIN_CNTL_2 0xc05001a4
smu_7_1_1_d.h 59 #define ixCG_CLKPIN_CNTL_2 0xc05001a4
smu_7_1_2_d.h 60 #define ixCG_CLKPIN_CNTL_2 0xc05001a4
smu_7_1_3_d.h 63 #define ixCG_CLKPIN_CNTL_2 0xc05001a4
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik.c 1775 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
1778 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data);
amdgpu_vi.c 342 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);

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