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    Searched refs:ixDIDT_DBR_EDC_STALL_PATTERN_5_6 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	7261 #define ixDIDT_DBR_EDC_STALL_PATTERN_5_6 0x0097
gc_9_1_offset.h	7466 #define ixDIDT_DBR_EDC_STALL_PATTERN_5_6 0x0097

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