1 /* $NetBSD: smu_7_0_0_d.h,v 1.3 2021/12/18 23:45:23 riastradh Exp $ */ 2 3 /* 4 * SMU_7_0_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef SMU_7_0_0_D_H 27 #define SMU_7_0_0_D_H 28 29 #define mmGCK_SMC_IND_INDEX 0x80 30 #define mmGCK0_GCK_SMC_IND_INDEX 0x80 31 #define mmGCK1_GCK_SMC_IND_INDEX 0x82 32 #define mmGCK2_GCK_SMC_IND_INDEX 0x84 33 #define mmGCK3_GCK_SMC_IND_INDEX 0x86 34 #define mmGCK_SMC_IND_DATA 0x81 35 #define mmGCK0_GCK_SMC_IND_DATA 0x81 36 #define mmGCK1_GCK_SMC_IND_DATA 0x83 37 #define mmGCK2_GCK_SMC_IND_DATA 0x85 38 #define mmGCK3_GCK_SMC_IND_DATA 0x87 39 #define ixCG_DCLK_CNTL 0xc050009c 40 #define ixCG_DCLK_STATUS 0xc05000a0 41 #define ixCG_VCLK_CNTL 0xc05000a4 42 #define ixCG_VCLK_STATUS 0xc05000a8 43 #define ixCG_ECLK_CNTL 0xc05000ac 44 #define ixCG_ECLK_STATUS 0xc05000b0 45 #define ixCG_ACLK_CNTL 0xc05000dc 46 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 47 #define ixCG_SPLL_FUNC_CNTL 0xc0500140 48 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 49 #define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 50 #define ixCG_SPLL_FUNC_CNTL_4 0xc050014c 51 #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 52 #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 53 #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 54 #define ixSPLL_CNTL_MODE 0xc0500160 55 #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 56 #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 57 #define ixMPLL_BYPASSCLK_SEL 0xc050019c 58 #define ixCG_CLKPIN_CNTL 0xc05001a0 59 #define ixCG_CLKPIN_CNTL_2 0xc05001a4 60 #define ixTHM_CLK_CNTL 0xc05001a8 61 #define ixMISC_CLK_CTRL 0xc05001ac 62 #define ixGCK_PLL_TEST_CNTL 0xc05001c0 63 #define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 64 #define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 65 #define mmSMC_IND_INDEX 0x80 66 #define mmSMC0_SMC_IND_INDEX 0x80 67 #define mmSMC1_SMC_IND_INDEX 0x82 68 #define mmSMC2_SMC_IND_INDEX 0x84 69 #define mmSMC3_SMC_IND_INDEX 0x86 70 #define mmSMC_IND_DATA 0x81 71 #define mmSMC0_SMC_IND_DATA 0x81 72 #define mmSMC1_SMC_IND_DATA 0x83 73 #define mmSMC2_SMC_IND_DATA 0x85 74 #define mmSMC3_SMC_IND_DATA 0x87 75 #define mmSMC_IND_INDEX_0 0x80 76 #define mmSMC_IND_DATA_0 0x81 77 #define mmSMC_IND_INDEX_1 0x82 78 #define mmSMC_IND_DATA_1 0x83 79 #define mmSMC_IND_INDEX_2 0x84 80 #define mmSMC_IND_DATA_2 0x85 81 #define mmSMC_IND_INDEX_3 0x86 82 #define mmSMC_IND_DATA_3 0x87 83 #define mmSMC_IND_INDEX_4 0x88 84 #define mmSMC_IND_DATA_4 0x89 85 #define mmSMC_IND_INDEX_5 0x8a 86 #define mmSMC_IND_DATA_5 0x8b 87 #define mmSMC_IND_INDEX_6 0x8c 88 #define mmSMC_IND_DATA_6 0x8d 89 #define mmSMC_IND_INDEX_7 0x8e 90 #define mmSMC_IND_DATA_7 0x8f 91 #define mmSMC_IND_ACCESS_CNTL 0x90 92 #define mmSMC_MESSAGE_0 0x94 93 #define mmSMC_RESP_0 0x95 94 #define mmSMC_MESSAGE_1 0x96 95 #define mmSMC_RESP_1 0x97 96 #define mmSMC_MESSAGE_2 0x98 97 #define mmSMC_RESP_2 0x99 98 #define mmSMC_MESSAGE_3 0x9a 99 #define mmSMC_RESP_3 0x9b 100 #define mmSMC_MESSAGE_4 0x9c 101 #define mmSMC_RESP_4 0x9d 102 #define mmSMC_MESSAGE_5 0x9e 103 #define mmSMC_RESP_5 0x9f 104 #define mmSMC_MESSAGE_6 0xa0 105 #define mmSMC_RESP_6 0xa1 106 #define mmSMC_MESSAGE_7 0xa2 107 #define mmSMC_RESP_7 0xa3 108 #define mmSMC_MSG_ARG_0 0xa4 109 #define mmSMC_MSG_ARG_1 0xa5 110 #define mmSMC_MSG_ARG_2 0xa6 111 #define mmSMC_MSG_ARG_3 0xa7 112 #define mmSMC_MSG_ARG_4 0xa8 113 #define mmSMC_MSG_ARG_5 0xa9 114 #define mmSMC_MSG_ARG_6 0xaa 115 #define mmSMC_MSG_ARG_7 0xab 116 #define mmSMC_MESSAGE_8 0xb5 117 #define mmSMC_RESP_8 0xb6 118 #define mmSMC_MESSAGE_9 0xb7 119 #define mmSMC_RESP_9 0xb8 120 #define mmSMC_MESSAGE_10 0xb9 121 #define mmSMC_RESP_10 0xba 122 #define mmSMC_MESSAGE_11 0xbb 123 #define mmSMC_RESP_11 0xbc 124 #define mmSMC_MSG_ARG_8 0xbd 125 #define mmSMC_MSG_ARG_9 0xbe 126 #define mmSMC_MSG_ARG_10 0xbf 127 #define mmSMC_MSG_ARG_11 0x91 128 #define ixSMC_SYSCON_RESET_CNTL 0x80000000 129 #define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 130 #define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 131 #define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c 132 #define ixSMC_SYSCON_MISC_CNTL 0x80000010 133 #define ixSMC_SYSCON_MSG_ARG_0 0x80000068 134 #define ixSMC_PC_C 0x80000370 135 #define ixSMC_SCRATCH9 0x80000424 136 #define mmCG_FPS_CNT 0x1a4 137 #define mmSMU_SMC_IND_INDEX 0x80 138 #define mmSMU0_SMU_SMC_IND_INDEX 0x80 139 #define mmSMU1_SMU_SMC_IND_INDEX 0x82 140 #define mmSMU2_SMU_SMC_IND_INDEX 0x84 141 #define mmSMU3_SMU_SMC_IND_INDEX 0x86 142 #define mmSMU_SMC_IND_DATA 0x81 143 #define mmSMU0_SMU_SMC_IND_DATA 0x81 144 #define mmSMU1_SMU_SMC_IND_DATA 0x83 145 #define mmSMU2_SMU_SMC_IND_DATA 0x85 146 #define mmSMU3_SMU_SMC_IND_DATA 0x87 147 #define ixRCU_UC_EVENTS 0xc0000004 148 #define ixRCU_MISC_CTRL 0xc0000010 149 #define ixCC_RCU_FUSES 0xc00c0000 150 #define ixCC_SMU_MISC_FUSES 0xc00c0004 151 #define ixCC_SCLK_VID_FUSES 0xc00c0008 152 #define ixCC_GIO_IOCCFG_FUSES 0xc00c000c 153 #define ixCC_GIO_IOC_FUSES 0xc00c0010 154 #define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c 155 #define ixCC_TST_ID_STRAPS 0xc00c0020 156 #define ixCC_FCTRL_FUSES 0xc00c0024 157 #define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 158 #define ixSMU_STATUS 0xe0003088 159 #define ixSMU_FIRMWARE 0xe00030a4 160 #define ixSMU_INPUT_DATA 0xe00030b8 161 #define ixSMU_EFUSE_0 0xc0100000 162 #define ixDPM_TABLE_1 0x3f000 163 #define ixDPM_TABLE_2 0x3f004 164 #define ixDPM_TABLE_3 0x3f008 165 #define ixDPM_TABLE_4 0x3f00c 166 #define ixDPM_TABLE_5 0x3f010 167 #define ixDPM_TABLE_6 0x3f014 168 #define ixDPM_TABLE_7 0x3f018 169 #define ixDPM_TABLE_8 0x3f01c 170 #define ixDPM_TABLE_9 0x3f020 171 #define ixDPM_TABLE_10 0x3f024 172 #define ixDPM_TABLE_11 0x3f028 173 #define ixDPM_TABLE_12 0x3f02c 174 #define ixDPM_TABLE_13 0x3f030 175 #define ixDPM_TABLE_14 0x3f034 176 #define ixDPM_TABLE_15 0x3f038 177 #define ixDPM_TABLE_16 0x3f03c 178 #define ixDPM_TABLE_17 0x3f040 179 #define ixDPM_TABLE_18 0x3f044 180 #define ixDPM_TABLE_19 0x3f048 181 #define ixDPM_TABLE_20 0x3f04c 182 #define ixDPM_TABLE_21 0x3f050 183 #define ixDPM_TABLE_22 0x3f054 184 #define ixDPM_TABLE_23 0x3f058 185 #define ixDPM_TABLE_24 0x3f05c 186 #define ixDPM_TABLE_25 0x3f060 187 #define ixDPM_TABLE_26 0x3f064 188 #define ixDPM_TABLE_27 0x3f068 189 #define ixDPM_TABLE_28 0x3f06c 190 #define ixDPM_TABLE_29 0x3f070 191 #define ixDPM_TABLE_30 0x3f074 192 #define ixDPM_TABLE_31 0x3f078 193 #define ixDPM_TABLE_32 0x3f07c 194 #define ixDPM_TABLE_33 0x3f080 195 #define ixDPM_TABLE_34 0x3f084 196 #define ixDPM_TABLE_35 0x3f088 197 #define ixDPM_TABLE_36 0x3f08c 198 #define ixDPM_TABLE_37 0x3f090 199 #define ixDPM_TABLE_38 0x3f094 200 #define ixDPM_TABLE_39 0x3f098 201 #define ixDPM_TABLE_40 0x3f09c 202 #define ixDPM_TABLE_41 0x3f0a0 203 #define ixDPM_TABLE_42 0x3f0a4 204 #define ixDPM_TABLE_43 0x3f0a8 205 #define ixDPM_TABLE_44 0x3f0ac 206 #define ixDPM_TABLE_45 0x3f0b0 207 #define ixDPM_TABLE_46 0x3f0b4 208 #define ixDPM_TABLE_47 0x3f0b8 209 #define ixDPM_TABLE_48 0x3f0bc 210 #define ixDPM_TABLE_49 0x3f0c0 211 #define ixDPM_TABLE_50 0x3f0c4 212 #define ixDPM_TABLE_51 0x3f0c8 213 #define ixDPM_TABLE_52 0x3f0cc 214 #define ixDPM_TABLE_53 0x3f0d0 215 #define ixDPM_TABLE_54 0x3f0d4 216 #define ixDPM_TABLE_55 0x3f0d8 217 #define ixDPM_TABLE_56 0x3f0dc 218 #define ixDPM_TABLE_57 0x3f0e0 219 #define ixDPM_TABLE_58 0x3f0e4 220 #define ixDPM_TABLE_59 0x3f0e8 221 #define ixDPM_TABLE_60 0x3f0ec 222 #define ixDPM_TABLE_61 0x3f0f0 223 #define ixDPM_TABLE_62 0x3f0f4 224 #define ixDPM_TABLE_63 0x3f0f8 225 #define ixDPM_TABLE_64 0x3f0fc 226 #define ixDPM_TABLE_65 0x3f100 227 #define ixDPM_TABLE_66 0x3f104 228 #define ixDPM_TABLE_67 0x3f108 229 #define ixDPM_TABLE_68 0x3f10c 230 #define ixDPM_TABLE_69 0x3f110 231 #define ixDPM_TABLE_70 0x3f114 232 #define ixDPM_TABLE_71 0x3f118 233 #define ixDPM_TABLE_72 0x3f11c 234 #define ixDPM_TABLE_73 0x3f120 235 #define ixDPM_TABLE_74 0x3f124 236 #define ixDPM_TABLE_75 0x3f128 237 #define ixDPM_TABLE_76 0x3f12c 238 #define ixDPM_TABLE_77 0x3f130 239 #define ixDPM_TABLE_78 0x3f134 240 #define ixDPM_TABLE_79 0x3f138 241 #define ixDPM_TABLE_80 0x3f13c 242 #define ixDPM_TABLE_81 0x3f140 243 #define ixDPM_TABLE_82 0x3f144 244 #define ixDPM_TABLE_83 0x3f148 245 #define ixDPM_TABLE_84 0x3f14c 246 #define ixDPM_TABLE_85 0x3f150 247 #define ixDPM_TABLE_86 0x3f154 248 #define ixDPM_TABLE_87 0x3f158 249 #define ixDPM_TABLE_88 0x3f15c 250 #define ixDPM_TABLE_89 0x3f160 251 #define ixDPM_TABLE_90 0x3f164 252 #define ixDPM_TABLE_91 0x3f168 253 #define ixDPM_TABLE_92 0x3f16c 254 #define ixDPM_TABLE_93 0x3f170 255 #define ixDPM_TABLE_94 0x3f174 256 #define ixDPM_TABLE_95 0x3f178 257 #define ixDPM_TABLE_96 0x3f17c 258 #define ixDPM_TABLE_97 0x3f180 259 #define ixDPM_TABLE_98 0x3f184 260 #define ixDPM_TABLE_99 0x3f188 261 #define ixDPM_TABLE_100 0x3f18c 262 #define ixDPM_TABLE_101 0x3f190 263 #define ixDPM_TABLE_102 0x3f194 264 #define ixDPM_TABLE_103 0x3f198 265 #define ixDPM_TABLE_104 0x3f19c 266 #define ixDPM_TABLE_105 0x3f1a0 267 #define ixDPM_TABLE_106 0x3f1a4 268 #define ixDPM_TABLE_107 0x3f1a8 269 #define ixDPM_TABLE_108 0x3f1ac 270 #define ixDPM_TABLE_109 0x3f1b0 271 #define ixDPM_TABLE_110 0x3f1b4 272 #define ixDPM_TABLE_111 0x3f1b8 273 #define ixDPM_TABLE_112 0x3f1bc 274 #define ixDPM_TABLE_113 0x3f1c0 275 #define ixDPM_TABLE_114 0x3f1c4 276 #define ixDPM_TABLE_115 0x3f1c8 277 #define ixDPM_TABLE_116 0x3f1cc 278 #define ixDPM_TABLE_117 0x3f1d0 279 #define ixDPM_TABLE_118 0x3f1d4 280 #define ixDPM_TABLE_119 0x3f1d8 281 #define ixDPM_TABLE_120 0x3f1dc 282 #define ixDPM_TABLE_121 0x3f1e0 283 #define ixDPM_TABLE_122 0x3f1e4 284 #define ixDPM_TABLE_123 0x3f1e8 285 #define ixDPM_TABLE_124 0x3f1ec 286 #define ixDPM_TABLE_125 0x3f1f0 287 #define ixDPM_TABLE_126 0x3f1f4 288 #define ixDPM_TABLE_127 0x3f1f8 289 #define ixDPM_TABLE_128 0x3f1fc 290 #define ixDPM_TABLE_129 0x3f200 291 #define ixDPM_TABLE_130 0x3f204 292 #define ixDPM_TABLE_131 0x3f208 293 #define ixDPM_TABLE_132 0x3f20c 294 #define ixDPM_TABLE_133 0x3f210 295 #define ixDPM_TABLE_134 0x3f214 296 #define ixDPM_TABLE_135 0x3f218 297 #define ixDPM_TABLE_136 0x3f21c 298 #define ixDPM_TABLE_137 0x3f220 299 #define ixDPM_TABLE_138 0x3f224 300 #define ixDPM_TABLE_139 0x3f228 301 #define ixDPM_TABLE_140 0x3f22c 302 #define ixDPM_TABLE_141 0x3f230 303 #define ixDPM_TABLE_142 0x3f234 304 #define ixDPM_TABLE_143 0x3f238 305 #define ixDPM_TABLE_144 0x3f23c 306 #define ixDPM_TABLE_145 0x3f240 307 #define ixDPM_TABLE_146 0x3f244 308 #define ixDPM_TABLE_147 0x3f248 309 #define ixDPM_TABLE_148 0x3f24c 310 #define ixDPM_TABLE_149 0x3f250 311 #define ixDPM_TABLE_150 0x3f254 312 #define ixDPM_TABLE_151 0x3f258 313 #define ixDPM_TABLE_152 0x3f25c 314 #define ixDPM_TABLE_153 0x3f260 315 #define ixDPM_TABLE_154 0x3f264 316 #define ixDPM_TABLE_155 0x3f268 317 #define ixDPM_TABLE_156 0x3f26c 318 #define ixDPM_TABLE_157 0x3f270 319 #define ixDPM_TABLE_158 0x3f274 320 #define ixDPM_TABLE_159 0x3f278 321 #define ixDPM_TABLE_160 0x3f27c 322 #define ixDPM_TABLE_161 0x3f280 323 #define ixDPM_TABLE_162 0x3f284 324 #define ixDPM_TABLE_163 0x3f288 325 #define ixDPM_TABLE_164 0x3f28c 326 #define ixDPM_TABLE_165 0x3f290 327 #define ixDPM_TABLE_166 0x3f294 328 #define ixDPM_TABLE_167 0x3f298 329 #define ixDPM_TABLE_168 0x3f29c 330 #define ixDPM_TABLE_169 0x3f2a0 331 #define ixDPM_TABLE_170 0x3f2a4 332 #define ixDPM_TABLE_171 0x3f2a8 333 #define ixDPM_TABLE_172 0x3f2ac 334 #define ixDPM_TABLE_173 0x3f2b0 335 #define ixDPM_TABLE_174 0x3f2b4 336 #define ixDPM_TABLE_175 0x3f2b8 337 #define ixDPM_TABLE_176 0x3f2bc 338 #define ixDPM_TABLE_177 0x3f2c0 339 #define ixDPM_TABLE_178 0x3f2c4 340 #define ixDPM_TABLE_179 0x3f2c8 341 #define ixDPM_TABLE_180 0x3f2cc 342 #define ixDPM_TABLE_181 0x3f2d0 343 #define ixDPM_TABLE_182 0x3f2d4 344 #define ixDPM_TABLE_183 0x3f2d8 345 #define ixDPM_TABLE_184 0x3f2dc 346 #define ixDPM_TABLE_185 0x3f2e0 347 #define ixDPM_TABLE_186 0x3f2e4 348 #define ixDPM_TABLE_187 0x3f2e8 349 #define ixDPM_TABLE_188 0x3f2ec 350 #define ixDPM_TABLE_189 0x3f2f0 351 #define ixDPM_TABLE_190 0x3f2f4 352 #define ixDPM_TABLE_191 0x3f2f8 353 #define ixSOFT_REGISTERS_TABLE_1 0x3f900 354 #define ixSOFT_REGISTERS_TABLE_2 0x3f904 355 #define ixSOFT_REGISTERS_TABLE_3 0x3f908 356 #define ixSOFT_REGISTERS_TABLE_4 0x3f90c 357 #define ixSOFT_REGISTERS_TABLE_5 0x3f910 358 #define ixSOFT_REGISTERS_TABLE_6 0x3f914 359 #define ixSOFT_REGISTERS_TABLE_7 0x3f918 360 #define ixSOFT_REGISTERS_TABLE_8 0x3f91c 361 #define ixSOFT_REGISTERS_TABLE_9 0x3f920 362 #define ixSOFT_REGISTERS_TABLE_10 0x3f924 363 #define ixSOFT_REGISTERS_TABLE_11 0x3f928 364 #define ixSOFT_REGISTERS_TABLE_12 0x3f92c 365 #define ixSOFT_REGISTERS_TABLE_13 0x3f930 366 #define ixSOFT_REGISTERS_TABLE_14 0x3f934 367 #define ixSOFT_REGISTERS_TABLE_15 0x3f938 368 #define ixSOFT_REGISTERS_TABLE_16 0x3f93c 369 #define ixSOFT_REGISTERS_TABLE_17 0x3f940 370 #define ixSOFT_REGISTERS_TABLE_18 0x3f944 371 #define ixSOFT_REGISTERS_TABLE_19 0x3f948 372 #define ixSOFT_REGISTERS_TABLE_20 0x3f94c 373 #define ixSOFT_REGISTERS_TABLE_21 0x3f950 374 #define ixSMU_LCLK_DPM_STATE_0_CNTL_0 0x3fd00 375 #define ixSMU_LCLK_DPM_STATE_1_CNTL_0 0x3fd14 376 #define ixSMU_LCLK_DPM_STATE_2_CNTL_0 0x3fd28 377 #define ixSMU_LCLK_DPM_STATE_3_CNTL_0 0x3fd3c 378 #define ixSMU_LCLK_DPM_STATE_4_CNTL_0 0x3fd50 379 #define ixSMU_LCLK_DPM_STATE_5_CNTL_0 0x3fd64 380 #define ixSMU_LCLK_DPM_STATE_6_CNTL_0 0x3fd78 381 #define ixSMU_LCLK_DPM_STATE_7_CNTL_0 0x3fd8c 382 #define ixSMU_LCLK_DPM_STATE_0_CNTL_1 0x3fd04 383 #define ixSMU_LCLK_DPM_STATE_1_CNTL_1 0x3fd18 384 #define ixSMU_LCLK_DPM_STATE_2_CNTL_1 0x3fd2c 385 #define ixSMU_LCLK_DPM_STATE_3_CNTL_1 0x3fd40 386 #define ixSMU_LCLK_DPM_STATE_4_CNTL_1 0x3fd54 387 #define ixSMU_LCLK_DPM_STATE_5_CNTL_1 0x3fd68 388 #define ixSMU_LCLK_DPM_STATE_6_CNTL_1 0x3fd7c 389 #define ixSMU_LCLK_DPM_STATE_7_CNTL_1 0x3fd90 390 #define ixSMU_LCLK_DPM_STATE_0_CNTL_2 0x3fd08 391 #define ixSMU_LCLK_DPM_STATE_1_CNTL_2 0x3fd1c 392 #define ixSMU_LCLK_DPM_STATE_2_CNTL_2 0x3fd30 393 #define ixSMU_LCLK_DPM_STATE_3_CNTL_2 0x3fd44 394 #define ixSMU_LCLK_DPM_STATE_4_CNTL_2 0x3fd58 395 #define ixSMU_LCLK_DPM_STATE_5_CNTL_2 0x3fd6c 396 #define ixSMU_LCLK_DPM_STATE_6_CNTL_2 0x3fd80 397 #define ixSMU_LCLK_DPM_STATE_7_CNTL_2 0x3fd94 398 #define ixSMU_LCLK_DPM_STATE_0_CNTL_3 0x3fd0c 399 #define ixSMU_LCLK_DPM_STATE_1_CNTL_3 0x3fd20 400 #define ixSMU_LCLK_DPM_STATE_2_CNTL_3 0x3fd34 401 #define ixSMU_LCLK_DPM_STATE_3_CNTL_3 0x3fd48 402 #define ixSMU_LCLK_DPM_STATE_4_CNTL_3 0x3fd5c 403 #define ixSMU_LCLK_DPM_STATE_5_CNTL_3 0x3fd70 404 #define ixSMU_LCLK_DPM_STATE_6_CNTL_3 0x3fd84 405 #define ixSMU_LCLK_DPM_STATE_7_CNTL_3 0x3fd98 406 #define ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD 0x3fd10 407 #define ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD 0x3fd24 408 #define ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD 0x3fd38 409 #define ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD 0x3fd4c 410 #define ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD 0x3fd60 411 #define ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD 0x3fd74 412 #define ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD 0x3fd88 413 #define ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD 0x3fd9c 414 #define ixGIO_PID_CONTROLLER_CNTL_0 0x3fda0 415 #define ixGIO_PID_CONTROLLER_CNTL_1 0x3fda4 416 #define ixGIO_PID_CONTROLLER_CNTL_2 0x3fda8 417 #define ixGIO_PID_CONTROLLER_CNTL_3 0x3fdac 418 #define ixGIO_PID_CONTROLLER_CNTL_4 0x3fdb0 419 #define ixGIO_PID_CONTROLLER_CNTL_5 0x3fdb4 420 #define ixGIO_PID_CONTROLLER_CNTL_6 0x3fdb8 421 #define ixGIO_PID_CONTROLLER_CNTL_7 0x3fdbc 422 #define ixGIO_PID_CONTROLLER_CNTL_8 0x3fdc0 423 #define ixSMU_LCLK_DPM_LEVEL_COUNT 0x3fdc4 424 #define ixSMU_LCLK_DPM_CNTL 0x3fdc8 425 #define ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE 0x3fdcc 426 #define ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL 0x3fdd0 427 #define ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS 0x3fdd4 428 #define ixPM_FUSES_1 0x3fa80 429 #define ixPM_FUSES_2 0x3fa84 430 #define ixPM_FUSES_3 0x3fa88 431 #define ixPM_FUSES_4 0x3fa8c 432 #define ixPM_FUSES_5 0x3fa90 433 #define ixPM_FUSES_6 0x3fa94 434 #define ixPM_FUSES_7 0x3fa98 435 #define ixPM_FUSES_8 0x3fa9c 436 #define ixPM_FUSES_9 0x3faa0 437 #define ixPM_FUSES_10 0x3faa4 438 #define ixPM_FUSES_11 0x3faa8 439 #define ixPM_FUSES_12 0x3faac 440 #define ixPM_FUSES_13 0x3fab0 441 #define ixPM_FUSES_14 0x3fab4 442 #define ixPM_FUSES_15 0x3fab8 443 #define ixPM_FUSES_16 0x3fabc 444 #define ixPM_FUSES_17 0x3fac0 445 #define ixPM_FUSES_18 0x3fac4 446 #define ixPM_FUSES_19 0x3fac8 447 #define ixPM_FUSES_20 0x3facc 448 #define ixPM_FUSES_21 0x3fad0 449 #define ixPM_FUSES_22 0x3fad4 450 #define ixPM_FUSES_23 0x3fad8 451 #define ixPM_FUSES_24 0x3fadc 452 #define ixPM_FUSES_25 0x3fae0 453 #define ixPM_FUSES_26 0x3fae4 454 #define ixPM_FUSES_27 0x3fae8 455 #define ixPM_FUSES_28 0x3faec 456 #define ixPM_FUSES_29 0x3faf0 457 #define ixPM_FUSES_30 0x3faf4 458 #define ixPM_FUSES_31 0x3faf8 459 #define ixPM_FUSES_32 0x3fafc 460 #define ixPM_FUSES_33 0x3fb00 461 #define ixPM_FUSES_34 0x3fb04 462 #define ixPM_FUSES_35 0x3fb08 463 #define ixPM_FUSES_36 0x3fb0c 464 #define ixPM_FUSES_37 0x3fb10 465 #define ixPM_FUSES_38 0x3fb14 466 #define ixPM_FUSES_39 0x3fb18 467 #define ixPM_FUSES_40 0x3fb1c 468 #define ixPM_FUSES_41 0x3fb20 469 #define ixPM_FUSES_42 0x3fb24 470 #define ixPM_FUSES_43 0x3fb28 471 #define ixPM_FUSES_44 0x3fb2c 472 #define ixPM_FUSES_45 0x3fb30 473 #define ixPM_FUSES_46 0x3fb34 474 #define ixPM_FUSES_47 0x3fb38 475 #define ixPM_FUSES_48 0x3fb3c 476 #define ixPM_FUSES_49 0x3fb40 477 #define ixPM_FUSES_50 0x3fb44 478 #define ixPM_FUSES_51 0x3fb48 479 #define ixPM_FUSES_52 0x3fb4c 480 #define ixPM_FUSES_53 0x3fb50 481 #define ixPM_FUSES_54 0x3fb54 482 #define ixPM_FUSES_55 0x3fb58 483 #define ixPM_FUSES_56 0x3fb5c 484 #define ixPM_FUSES_57 0x3fb60 485 #define ixPM_FUSES_58 0x3fb64 486 #define ixPM_FUSES_59 0x3fb68 487 #define ixPM_FUSES_60 0x3fb6c 488 #define ixPM_FUSES_61 0x3fb70 489 #define ixPM_FUSES_62 0x3fb74 490 #define ixPM_FUSES_63 0x3fb78 491 #define ixPM_FUSES_64 0x3fb7c 492 #define ixPM_FUSES_65 0x3fb80 493 #define ixFIRMWARE_FLAGS 0x3f800 494 #define ixTEMPERATURE_READ_ADDR 0x3f808 495 #define ixCURRENT_GNB_TEMP 0x3f810 496 #define ixCURRENT_GLOBAL_TEMP 0x3f814 497 #define ixFEATURE_STATUS 0x3f818 498 #define ixPCIE_PLL_RECONF 0x3f81c 499 #define ixPM_INTERVAL_CNTL_0 0x3f820 500 #define ixPM_INTERVAL_CNTL_1 0x3f824 501 #define ixPM_INTERVAL_CNTL_2 0x3f82c 502 #define ixVPC_INTERVAL_CNTL 0x3f830 503 #define ixDISP_PHY_TDP_LIMIT 0x3f834 504 #define ixFCH_PWR_CREDIT 0x3f838 505 #define ixPKGPWR_MV_AVG 0x3f83c 506 #define ixPACKAGE_POWER 0x3f840 507 #define ixPKG_PWR_CNTL 0x3f844 508 #define ixPKG_PWR_STATUS 0x3f848 509 #define ixDISP_PHY_CONFIG 0x3f84c 510 #define ixGPU_TDP_LIMIT 0x3f850 511 #define ixEXT_API_IN_DATA_0_0 0x3f858 512 #define ixEXT_API_IN_DATA_0_1 0x3f85c 513 #define ixEXT_API_IN_DATA_0_2 0x3f860 514 #define ixEXT_API_IN_DATA_0_3 0x3f864 515 #define ixEXT_API_OUT_DATA_0_0 0x3f868 516 #define ixEXT_API_OUT_DATA_0_1 0x3f86c 517 #define ixEXT_API_OUT_DATA_0_2 0x3f870 518 #define ixEXT_API_OUT_DATA_0_3 0x3f874 519 #define ixBAPM_PARAMETERS 0x3f984 520 #define ixBAPM_PARAMETERS_2 0x3f988 521 #define ixBAPM_PARAMETERS_3 0x3f98c 522 #define ixBAPM_PARAMETERS_4 0x3f990 523 #define ixSMU_SVI_TELEMETRY 0x3f994 524 #define ixBAPM_STATUS 0x3f998 525 #define ixSMU_HTC_STATUS 0x3f99c 526 #define ixSMU_VPC_STATUS 0x3f9a0 527 #define ixENTITY_TEMPERATURES_1 0x3f9a4 528 #define ixENTITY_TEMPERATURES_2 0x3f9a8 529 #define ixENTITY_TEMPERATURES_3 0x3f9ac 530 #define ixCU_POWER 0x3f9b0 531 #define ixGPU_POWER 0x3f9b4 532 #define ixNTE_POWER 0x3f9b8 533 #define ixTDC_STATUS 0x3f9d0 534 #define ixTDC_MV_AVERAGE 0x3f9d4 535 #define ixPM_CONFIG 0x3f9d8 536 #define ixTE0_TEMPERATURE_READ_ADDR 0x3f9dc 537 #define ixTE1_TEMPERATURE_READ_ADDR 0x3f9e0 538 #define ixTE2_TEMPERATURE_READ_ADDR 0x3f9e4 539 #define ixNB_DPM_CONFIG_1 0x3f9e8 540 #define ixNB_DPM_CONFIG_2 0x3f9ec 541 #define ixNB_DPM_CONFIG_3 0x3f9f0 542 #define ixSMU_IDD_OVERRIDE 0x3f9fc 543 #define ixAVS_CONFIG 0x3fa00 544 #define ixTDC_VRM_LIMIT 0x3fa04 545 #define ixCU0_PSM_CONFIG 0x3fa08 546 #define ixCU1_PSM_CONFIG 0x3fa0c 547 #define ixSPMI_CONFIG 0x3fa10 548 #define ixSPMI_SMC_CHAIN_ADDR 0x3fa14 549 #define ixSPMI_STATUS 0x3fa30 550 #define ixAVSNB_CONFIG 0x3fa34 551 #define ixHTC_CONFIG 0x3fa38 552 #define ixAVS_CU0_TEMPERATURE_SENSOR 0x3fa3c 553 #define ixAVS_CU1_TEMPERATURE_SENSOR 0x3fa40 554 #define ixAVS_GNB_TEMPERATURE_SENSOR 0x3fa44 555 #define ixAVS_UNB_TEMPERATURE_SENSOR 0x3fa48 556 #define ixSMU_MONITOR_PORT80_MMIO_ADDR 0x3fa4c 557 #define ixSMU_MONITOR_PORT80_MEMBASE_HI 0x3fa50 558 #define ixSMU_MONITOR_PORT80_MEMBASE_LO 0x3fa54 559 #define ixSMU_MONITOR_PORT80_MEMSETUP 0x3fa58 560 #define ixSMU_MONITOR_PORT80_CTRL 0x3fa5c 561 #define ixSMU_TCEN_ALIVE 0x3fa60 562 #define ixPDM_STATUS 0x3fa64 563 #define ixPDM_CNTL_1 0x3fa68 564 #define ixPDM_CNTL_2 0x3fa6c 565 #define ixPDM_CNTL_3 0x3fa70 566 #define ixSMU_PM_STATUS_0 0x3fe00 567 #define ixSMU_PM_STATUS_1 0x3fe04 568 #define ixSMU_PM_STATUS_2 0x3fe08 569 #define ixSMU_PM_STATUS_3 0x3fe0c 570 #define ixSMU_PM_STATUS_4 0x3fe10 571 #define ixSMU_PM_STATUS_5 0x3fe14 572 #define ixSMU_PM_STATUS_6 0x3fe18 573 #define ixSMU_PM_STATUS_7 0x3fe1c 574 #define ixSMU_PM_STATUS_8 0x3fe20 575 #define ixSMU_PM_STATUS_9 0x3fe24 576 #define ixSMU_PM_STATUS_10 0x3fe28 577 #define ixSMU_PM_STATUS_11 0x3fe2c 578 #define ixSMU_PM_STATUS_12 0x3fe30 579 #define ixSMU_PM_STATUS_13 0x3fe34 580 #define ixSMU_PM_STATUS_14 0x3fe38 581 #define ixSMU_PM_STATUS_15 0x3fe3c 582 #define ixSMU_PM_STATUS_16 0x3fe40 583 #define ixSMU_PM_STATUS_17 0x3fe44 584 #define ixSMU_PM_STATUS_18 0x3fe48 585 #define ixSMU_PM_STATUS_19 0x3fe4c 586 #define ixSMU_PM_STATUS_20 0x3fe50 587 #define ixSMU_PM_STATUS_21 0x3fe54 588 #define ixSMU_PM_STATUS_22 0x3fe58 589 #define ixSMU_PM_STATUS_23 0x3fe5c 590 #define ixSMU_PM_STATUS_24 0x3fe60 591 #define ixSMU_PM_STATUS_25 0x3fe64 592 #define ixSMU_PM_STATUS_26 0x3fe68 593 #define ixSMU_PM_STATUS_27 0x3fe6c 594 #define ixSMU_PM_STATUS_28 0x3fe70 595 #define ixSMU_PM_STATUS_29 0x3fe74 596 #define ixSMU_PM_STATUS_30 0x3fe78 597 #define ixSMU_PM_STATUS_31 0x3fe7c 598 #define ixSMU_PM_STATUS_32 0x3fe80 599 #define ixSMU_PM_STATUS_33 0x3fe84 600 #define ixSMU_PM_STATUS_34 0x3fe88 601 #define ixSMU_PM_STATUS_35 0x3fe8c 602 #define ixSMU_PM_STATUS_36 0x3fe90 603 #define ixSMU_PM_STATUS_37 0x3fe94 604 #define ixSMU_PM_STATUS_38 0x3fe98 605 #define ixSMU_PM_STATUS_39 0x3fe9c 606 #define ixSMU_PM_STATUS_40 0x3fea0 607 #define ixSMU_PM_STATUS_41 0x3fea4 608 #define ixSMU_PM_STATUS_42 0x3fea8 609 #define ixSMU_PM_STATUS_43 0x3feac 610 #define ixSMU_PM_STATUS_44 0x3feb0 611 #define ixSMU_PM_STATUS_45 0x3feb4 612 #define ixSMU_PM_STATUS_46 0x3feb8 613 #define ixSMU_PM_STATUS_47 0x3febc 614 #define ixSMU_PM_STATUS_48 0x3fec0 615 #define ixSMU_PM_STATUS_49 0x3fec4 616 #define ixSMU_PM_STATUS_50 0x3fec8 617 #define ixSMU_PM_STATUS_51 0x3fecc 618 #define ixSMU_PM_STATUS_52 0x3fed0 619 #define ixSMU_PM_STATUS_53 0x3fed4 620 #define ixSMU_PM_STATUS_54 0x3fed8 621 #define ixSMU_PM_STATUS_55 0x3fedc 622 #define ixSMU_PM_STATUS_56 0x3fee0 623 #define ixSMU_PM_STATUS_57 0x3fee4 624 #define ixSMU_PM_STATUS_58 0x3fee8 625 #define ixSMU_PM_STATUS_59 0x3feec 626 #define ixSMU_PM_STATUS_60 0x3fef0 627 #define ixSMU_PM_STATUS_61 0x3fef4 628 #define ixSMU_PM_STATUS_62 0x3fef8 629 #define ixSMU_PM_STATUS_63 0x3fefc 630 #define ixSMU_PM_STATUS_64 0x3ff00 631 #define ixSMU_PM_STATUS_65 0x3ff04 632 #define ixSMU_PM_STATUS_66 0x3ff08 633 #define ixSMU_PM_STATUS_67 0x3ff0c 634 #define ixSMU_PM_STATUS_68 0x3ff10 635 #define ixSMU_PM_STATUS_69 0x3ff14 636 #define ixSMU_PM_STATUS_70 0x3ff18 637 #define ixSMU_PM_STATUS_71 0x3ff1c 638 #define ixSMU_PM_STATUS_72 0x3ff20 639 #define ixSMU_PM_STATUS_73 0x3ff24 640 #define ixSMU_PM_STATUS_74 0x3ff28 641 #define ixSMU_PM_STATUS_75 0x3ff2c 642 #define ixSMU_PM_STATUS_76 0x3ff30 643 #define ixSMU_PM_STATUS_77 0x3ff34 644 #define ixSMU_PM_STATUS_78 0x3ff38 645 #define ixSMU_PM_STATUS_79 0x3ff3c 646 #define ixSMU_PM_STATUS_80 0x3ff40 647 #define ixSMU_PM_STATUS_81 0x3ff44 648 #define ixSMU_PM_STATUS_82 0x3ff48 649 #define ixSMU_PM_STATUS_83 0x3ff4c 650 #define ixSMU_PM_STATUS_84 0x3ff50 651 #define ixSMU_PM_STATUS_85 0x3ff54 652 #define ixSMU_PM_STATUS_86 0x3ff58 653 #define ixSMU_PM_STATUS_87 0x3ff5c 654 #define ixSMU_PM_STATUS_88 0x3ff60 655 #define ixSMU_PM_STATUS_89 0x3ff64 656 #define ixSMU_PM_STATUS_90 0x3ff68 657 #define ixSMU_PM_STATUS_91 0x3ff6c 658 #define ixSMU_PM_STATUS_92 0x3ff70 659 #define ixSMU_PM_STATUS_93 0x3ff74 660 #define ixSMU_PM_STATUS_94 0x3ff78 661 #define ixSMU_PM_STATUS_95 0x3ff7c 662 #define ixSMU_PM_STATUS_96 0x3ff80 663 #define ixSMU_PM_STATUS_97 0x3ff84 664 #define ixSMU_PM_STATUS_98 0x3ff88 665 #define ixSMU_PM_STATUS_99 0x3ff8c 666 #define ixSMU_PM_STATUS_100 0x3ff90 667 #define ixSMU_PM_STATUS_101 0x3ff94 668 #define ixSMU_PM_STATUS_102 0x3ff98 669 #define ixSMU_PM_STATUS_103 0x3ff9c 670 #define ixSMU_PM_STATUS_104 0x3ffa0 671 #define ixSMU_PM_STATUS_105 0x3ffa4 672 #define ixSMU_PM_STATUS_106 0x3ffa8 673 #define ixSMU_PM_STATUS_107 0x3ffac 674 #define ixSMU_PM_STATUS_108 0x3ffb0 675 #define ixSMU_PM_STATUS_109 0x3ffb4 676 #define ixSMU_PM_STATUS_110 0x3ffb8 677 #define ixSMU_PM_STATUS_111 0x3ffbc 678 #define ixSMU_PM_STATUS_112 0x3ffc0 679 #define ixSMU_PM_STATUS_113 0x3ffc4 680 #define ixSMU_PM_STATUS_114 0x3ffc8 681 #define ixSMU_PM_STATUS_115 0x3ffcc 682 #define ixSMU_PM_STATUS_116 0x3ffd0 683 #define ixSMU_PM_STATUS_117 0x3ffd4 684 #define ixSMU_PM_STATUS_118 0x3ffd8 685 #define ixSMU_PM_STATUS_119 0x3ffdc 686 #define ixSMU_PM_STATUS_120 0x3ffe0 687 #define ixSMU_PM_STATUS_121 0x3ffe4 688 #define ixSMU_PM_STATUS_122 0x3ffe8 689 #define ixSMU_PM_STATUS_123 0x3ffec 690 #define ixSMU_PM_STATUS_124 0x3fff0 691 #define ixSMU_PM_STATUS_125 0x3fff4 692 #define ixSMU_PM_STATUS_126 0x3fff8 693 #define ixSMU_PM_STATUS_127 0x3fffc 694 #define ixCG_THERMAL_INT_ENA 0xc2100024 695 #define ixCG_THERMAL_INT_CTRL 0xc2100028 696 #define ixCG_THERMAL_INT_STATUS 0xc210002c 697 #define ixGENERAL_PWRMGT 0xc0200000 698 #define ixCNB_PWRMGT_CNTL 0xc0200004 699 #define ixSCLK_PWRMGT_CNTL 0xc0200008 700 #define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 701 #define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 702 #define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac 703 #define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 704 #define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 705 #define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 706 #define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc 707 #define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 708 #define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 709 #define ixPLL_TEST_CNTL 0xc020003c 710 #define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 711 #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 712 #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 713 #define ixCG_ACPI_CNTL 0xc0200064 714 #define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 715 #define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 716 #define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c 717 #define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 718 #define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c 719 #define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 720 #define ixSMU_VOLTAGE_STATUS 0xc0200094 721 #define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 722 #define ixCG_ULV_PARAMETER 0xc020015c 723 #define ixSCLK_MIN_DIV 0xc0200308 724 #define ixLCAC_SX0_CNTL 0xc0400d00 725 #define ixLCAC_SX0_OVR_SEL 0xc0400d04 726 #define ixLCAC_SX0_OVR_VAL 0xc0400d08 727 #define ixLCAC_MC0_CNTL 0xc0400d30 728 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 729 #define ixLCAC_MC0_OVR_VAL 0xc0400d38 730 #define ixLCAC_MC1_CNTL 0xc0400d3c 731 #define ixLCAC_MC1_OVR_SEL 0xc0400d40 732 #define ixLCAC_MC1_OVR_VAL 0xc0400d44 733 #define ixLCAC_MC2_CNTL 0xc0400d48 734 #define ixLCAC_MC2_OVR_SEL 0xc0400d4c 735 #define ixLCAC_MC2_OVR_VAL 0xc0400d50 736 #define ixLCAC_MC3_CNTL 0xc0400d54 737 #define ixLCAC_MC3_OVR_SEL 0xc0400d58 738 #define ixLCAC_MC3_OVR_VAL 0xc0400d5c 739 #define ixLCAC_CPL_CNTL 0xc0400d80 740 #define ixLCAC_CPL_OVR_SEL 0xc0400d84 741 #define ixLCAC_CPL_OVR_VAL 0xc0400d88 742 743 #endif /* SMU_7_0_0_D_H */ 744
Indexes created Sat Nov 08 18:09:48 GMT 2025