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Searched refs:ixGCK_DFS_BYPASS_CNTL (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_polaris_baco.c	`70 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL }, 162 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL },`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v4_0.c	`883 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 890 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);`
amdgpu_uvd_v7_0.c	`1687 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 1696 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_d.h	`46 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118`
smu_7_0_1_d.h	`46 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118`
smu_7_1_0_d.h	`46 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118`
smu_7_1_1_d.h	`46 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118`
smu_7_1_2_d.h	`46 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118`
smu_7_1_3_d.h	`49 #define ixGCK_DFS_BYPASS_CNTL 0xc0500118`

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