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Searched refs:ixLCAC_MC0_CNTL (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_6_0_d.h	`28 #define ixLCAC_MC0_CNTL 0x011C`
smu_8_0_d.h	`634 #define ixLCAC_MC0_CNTL 0xd0208130`
smu_7_0_0_d.h	`727 #define ixLCAC_MC0_CNTL 0xc0400d30`
smu_7_0_1_d.h	`1217 #define ixLCAC_MC0_CNTL 0xc0400d30`
smu_7_1_0_d.h	`1246 #define ixLCAC_MC0_CNTL 0xc0400d30`
smu_7_1_1_d.h	`1027 #define ixLCAC_MC0_CNTL 0xc0400130`
smu_7_1_2_d.h	`1178 #define ixLCAC_MC0_CNTL 0xc0400130`
smu_7_1_3_d.h	`1110 #define ixLCAC_MC0_CNTL 0xc0400130`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_hwmgr.c	`1129 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); 1134 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009); 1137 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);`

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