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    Searched refs:ixLCAC_MC1_OVR_SEL (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_6_0_d.h 32 #define ixLCAC_MC1_OVR_SEL 0x0120
smu_8_0_d.h 638 #define ixLCAC_MC1_OVR_SEL 0xd0208140
smu_7_0_0_d.h 731 #define ixLCAC_MC1_OVR_SEL 0xc0400d40
smu_7_0_1_d.h 1221 #define ixLCAC_MC1_OVR_SEL 0xc0400d40
smu_7_1_0_d.h 1250 #define ixLCAC_MC1_OVR_SEL 0xc0400d40
smu_7_1_1_d.h 1031 #define ixLCAC_MC1_OVR_SEL 0xc0400140
smu_7_1_2_d.h 1182 #define ixLCAC_MC1_OVR_SEL 0xc0400140
smu_7_1_3_d.h 1114 #define ixLCAC_MC1_OVR_SEL 0xc0400140
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_kv_dpm.c 547 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);

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