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    Searched refs:ixLCAC_MC3_OVR_SEL (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_6_0_d.h 38 #define ixLCAC_MC3_OVR_SEL 0x0126
smu_8_0_d.h 644 #define ixLCAC_MC3_OVR_SEL 0xd0208158
smu_7_0_0_d.h 737 #define ixLCAC_MC3_OVR_SEL 0xc0400d58
smu_7_0_1_d.h 1227 #define ixLCAC_MC3_OVR_SEL 0xc0400d58
smu_7_1_0_d.h 1256 #define ixLCAC_MC3_OVR_SEL 0xc0400d58
smu_7_1_1_d.h 1037 #define ixLCAC_MC3_OVR_SEL 0xc0400158
smu_7_1_2_d.h 1188 #define ixLCAC_MC3_OVR_SEL 0xc0400158
smu_7_1_3_d.h 1120 #define ixLCAC_MC3_OVR_SEL 0xc0400158
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_kv_dpm.c 555 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);

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